MEC probably doesn't support EVENT_WRITE_EOP.
Both PAL and RadeonSI use RELEASE_MEM.
RADV used RELEASE_MEM too but "is_gfx8_mec" was very misleading.
This commit just cleans that up. No functional changes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
EOS events are buggy on GFX7 and can cause hangs when used
together in the same IB with CP DMA packets that use L2.
While we don't use the L2 for CP DMA copies, we still use it
with CP DMA prefetches, so the issue needs to be mitigated.
As a mitigation, avoid using EVENT_WRITE_EOS and prefer to use
the BOTTOM_OF_PIPE event instead of PS_DONE/CS_DONE, which should
be close enough.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
radeon_cmdbuf is too low level for stuff like tracked registers and
buffered registers on GFX11+.
This commit introduces radv_cmd_stream which is defined like:
struct radv_cmd_stream {
struct radeon_cmdbuf *b;
// TODO: add tracked regs
// TODO: add buffered regs
};
It will be much easier/cleaner to implement tracked/buffered registers
with this new structure.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36314>
A begin/end sequence is something like (it's all macros based):
radeon_begin(cs);
radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
radeon_emit(vertex_count);
radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);
radeon_end();
This is loosely based on RadeonSI (see !8653 (a0978fff)) and it seems
indeed faster overall.
The main goal of this rework is to re-use the same logic as RadeonSI
for paired packets on GFX12 (also GFX11 dGPUs) because it's supposed
to be way faster, especially on GFX12 where the CP is slow. The other
goal is to share more cmdbuf emission between both drivers in the near
future.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34229>
Timur Kristóf