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radv: move context_roll_without_scissor_emitted to radv_cmd_stream

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36314>
This commit is contained in:
Samuel Pitoiset
2025-07-23 14:48:27 +02:00
committed by Marge Bot
parent cc85f33b57
commit e2def79e2a
4 changed files with 14 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+6 -6
View File
@@ -4109,7 +4109,7 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer, const struct
radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.render.ds_att.ds, iview, false);
}
cmd_buffer->state.context_roll_without_scissor_emitted = true;
cmd_buffer->cs->context_roll_without_scissor_emitted = true;
}
/**
@@ -4365,7 +4365,7 @@ radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, struct ra
assert(cs->b->cdw <= cdw_max);
cmd_buffer->state.context_roll_without_scissor_emitted = true;
cmd_buffer->cs->context_roll_without_scissor_emitted = true;
}
/**
@@ -10217,7 +10217,7 @@ radv_get_needed_dynamic_states(struct radv_cmd_buffer *cmd_buffer)
static bool
radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info)
{
if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_va)
if (cmd_buffer->cs->context_roll_without_scissor_emitted || info->strmout_va)
return true;
uint64_t used_dynamic_states = radv_get_needed_dynamic_states(cmd_buffer);
@@ -11406,7 +11406,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
if (late_scissor_emission) {
radv_emit_scissor(cmd_buffer);
cmd_buffer->state.context_roll_without_scissor_emitted = false;
cmd_buffer->cs->context_roll_without_scissor_emitted = false;
}
}
@@ -14049,7 +14049,7 @@ radv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstC
*/
radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, sb[i].size >> 2);
cmd_buffer->state.context_roll_without_scissor_emitted = true;
cmd_buffer->cs->context_roll_without_scissor_emitted = true;
if (append) {
radeon_emit(PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
@@ -14168,7 +14168,7 @@ radv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCou
*/
radeon_set_context_reg(R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16 * i, 0);
cmd_buffer->state.context_roll_without_scissor_emitted = true;
cmd_buffer->cs->context_roll_without_scissor_emitted = true;
}
radeon_end();
src/amd/vulkan/radv_cmd_buffer.h
+2 -2
View File
@@ -453,8 +453,6 @@ struct radv_cmd_state {
bool inherited_occlusion_queries;
VkQueryControlFlags inherited_query_control_flags;
bool context_roll_without_scissor_emitted;
/* SQTT related state. */
uint32_t current_event_type;
uint32_t num_events;
@@ -563,6 +561,8 @@ struct gfx12_reg {
struct radv_cmd_stream {
struct radeon_cmdbuf *b;
bool context_roll_without_scissor_emitted;
uint32_t num_buffered_sh_regs;
struct {
struct gfx12_reg buffered_sh_regs[64];
src/amd/vulkan/radv_cs.c
+1
View File
@@ -630,6 +630,7 @@ radv_cs_write_data_imm(struct radv_cmd_stream *cs, unsigned engine_sel, uint64_t
static void
radv_init_cmd_stream(struct radv_cmd_stream *cs)
{
cs->context_roll_without_scissor_emitted = false;
cs->num_buffered_sh_regs = 0;
}
src/amd/vulkan/radv_cs.h
+5 -5
View File
@@ -90,7 +90,7 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned
radeon_set_context_reg(reg, __value); \
BITSET_SET(__tracked_regs->reg_saved_mask, (reg_enum)); \
__tracked_regs->reg_value[(reg_enum)] = __value; \
__cmdbuf->state.context_roll_without_scissor_emitted = true; \
__cmdbuf->cs->context_roll_without_scissor_emitted = true; \
} \
} while (0)
@@ -107,7 +107,7 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned
BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1); \
__tracked_regs->reg_value[(reg_enum)] = __v1; \
__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
cmdbuf->state.context_roll_without_scissor_emitted = true; \
cmdbuf->cs->context_roll_without_scissor_emitted = true; \
} \
} while (0)
@@ -127,7 +127,7 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned
__tracked_regs->reg_value[(reg_enum)] = __v1; \
__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
__tracked_regs->reg_value[(reg_enum) + 2] = __v3; \
cmdbuf->state.context_roll_without_scissor_emitted = true; \
cmdbuf->cs->context_roll_without_scissor_emitted = true; \
} \
} while (0)
@@ -149,7 +149,7 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned
__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
__tracked_regs->reg_value[(reg_enum) + 2] = __v3; \
__tracked_regs->reg_value[(reg_enum) + 3] = __v4; \
cmdbuf->state.context_roll_without_scissor_emitted = true; \
cmdbuf->cs->context_roll_without_scissor_emitted = true; \
} \
} while (0)
@@ -160,7 +160,7 @@ radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned
radeon_set_context_reg_seq(reg, num); \
radeon_emit_array(values, num); \
memcpy(saved_values, values, sizeof(uint32_t) * (num)); \
__cmdbuf->state.context_roll_without_scissor_emitted = true; \
__cmdbuf->cs->context_roll_without_scissor_emitted = true; \
} \
} while (0)