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18780 Commits

Author SHA1 Message Date
Georg Lehmann 8e03505782 aco: don't insert s_sendmsg dealloc_vgprs with little vgprs allocated 
Reduces message bus traffic when the benefit is small.

Foz-DB Navi31:
Totals from 3752 (4.67% of 80273) affected shaders:
Instrs: 1999755 -> 1992249 (-0.38%)
CodeSize: 10531824 -> 10501800 (-0.29%)
Latency: 14935247 -> 14935147 (-0.00%)
InvThroughput: 5976053 -> 5975262 (-0.01%)

Foz-DB Navi33:
Totals from 2614 (3.26% of 80273) affected shaders:
Instrs: 969475 -> 964247 (-0.54%)
CodeSize: 5171240 -> 5150328 (-0.40%)
Latency: 7891519 -> 7891434 (-0.00%)
InvThroughput: 4815008 -> 4814287 (-0.01%); split: -0.01%, +0.00%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37508>
 2025-09-26 07:51:02 +00:00
Georg Lehmann 27cc6317f9 aco: dealloc vgprs if there is a pending non scratch store and no pending export 
Because s_sendmsg dealloc_vgprs waits for every counter except vs_count,
and the message bus has limited throughput, we should only insert the dealloc
when we know that it's beneficial.

Foz-DB Navi31:
Totals from 5280 (6.58% of 80273) affected shaders:
Instrs: 4186851 -> 4197416 (+0.25%)
CodeSize: 21910004 -> 21952264 (+0.19%)
Latency: 31679067 -> 31679173 (+0.00%)
InvThroughput: 9182625 -> 9183417 (+0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37508>
 2025-09-26 07:51:02 +00:00
Georg Lehmann 26e041e821 aco: remove existing dealloc_vgprs use 
We didn't consider that s_sendmsg dealloc_vgpr waits for all counters
expect vscnt.

Foz-DB Navi31:
Totals from 74090 (92.52% of 80084) affected shaders:
Instrs: 36031071 -> 35853573 (-0.49%)
CodeSize: 189233756 -> 188523764 (-0.38%)
Latency: 222378318 -> 222374890 (-0.00%)
InvThroughput: 33366893 -> 33362457 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37508>
 2025-09-26 07:51:02 +00:00
Georg Lehmann cf30742a66 radv,aco: don't end monolithic ray tracing with unconditional terminate 
The terminate requires more code and blocks us from deallocating VGPRs early.

Foz-DB Navi31:
Totals from 63 (0.08% of 80273) affected shaders:
Instrs: 3372702 -> 3372467 (-0.01%)
CodeSize: 17441676 -> 17440736 (-0.01%)
Latency: 19763447 -> 19763288 (-0.00%)
InvThroughput: 3860502 -> 3860478 (-0.00%)
Branches: 96204 -> 96141 (-0.07%)
SALU: 406648 -> 406549 (-0.02%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37542>
 2025-09-25 15:35:55 +00:00
Daniel Schürmann d041640b88 aco: remove excess offset handling for load/store_shared 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37453>
 2025-09-24 14:28:25 +00:00
Daniel Schürmann dbb20a4e23 aco/optimizer: remove DS offset optimization 
No fossil changes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37453>
 2025-09-24 14:28:24 +00:00
Daniel Schürmann 10266e7b21 radv: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets 
Totals from 76 (0.10% of 79839) affected shaders: (Navi48)

Instrs: 237450 -> 237323 (-0.05%); split: -0.05%, +0.00%
CodeSize: 1276732 -> 1275824 (-0.07%); split: -0.07%, +0.00%
Latency: 1123467 -> 1123387 (-0.01%); split: -0.01%, +0.01%
InvThroughput: 364942 -> 364738 (-0.06%); split: -0.06%, +0.00%
Copies: 20654 -> 20636 (-0.09%); split: -0.09%, +0.00%
Branches: 7326 -> 7327 (+0.01%)
PreSGPRs: 5197 -> 5195 (-0.04%)
PreVGPRs: 3395 -> 3396 (+0.03%)
VALU: 96134 -> 96034 (-0.10%)
SALU: 48059 -> 48041 (-0.04%); split: -0.04%, +0.00%
VOPD: 10 -> 8 (-20.00%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37453>
 2025-09-24 14:28:24 +00:00
Rhys Perry 591b498e1f radv: fix progress reporting in lower_rt_derefs 
Only create nir_load_rt_arg_scratch_offset_amd if needed.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:27 +00:00
Rhys Perry 92a2ab8b64 ac/nir: fix progress reporting in ac_nir_lower_tex 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:27 +00:00
Natalie Vock f0d3d0ad21 aco/scheduler: Bail early on unreorderable instructions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37212>
 2025-09-22 11:13:50 +00:00
Ali, Nawwar c75cb1233c amd/vpelib: add FL capabilitie and lut container size 
[WHY]
get a clear definition of fastload support and actual 3d lut
container size

[HOW]
Added related code

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Nawwar Ali <Nawwar.Ali@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37504>
 2025-09-22 10:37:22 +00:00
Nagulendran, Iswara 1cd047c958 amd/vpelib: Handle Destination Rect with zero dimensions 
[Why]
Route case where dest rect has
zero dimensions to perform background
color fill.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37504>
 2025-09-22 10:37:22 +00:00
Assadian, Navid 4c96e8c352 amd/vpelib: Add new colors to visual confirm 
[WHY]
Newly added formats require distinct colors for proper differentiation.

[HOW]
Add new colors, pairwise distinguishable for newly added formats.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Navid Assadian <Navid.Assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37504>
 2025-09-22 10:37:21 +00:00
swscm, z1 d79665066d amd/vpelib: Ensures type-safe comparison for callback assignment 
[WHY & How]
Ensures type-safe comparison for the sys_event callback assignment by
casting the NULL constant to the appropriate function pointer type.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37504>
 2025-09-22 10:37:21 +00:00
Zhao, Jiali 237ab0778e amd/vpelib: Create Function to Check for Blending Feature 
[HOW]
Created check_blending_support function and condition to check for
readable purpose

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Zhao, Jiali <Jiali.Zhao@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37504>
 2025-09-22 10:37:21 +00:00
Marek Olšák bbab69d343 radv: fix load_smem alignment 
radv_cmd_buffer_upload_alloc_aligned is used with alignment=0, which
guarantees that the alignment is at least 4.

Fixes: 9e16ed7a13 - ac/nir: switch nir_load_smem_amd uses to ac_nir_load_smem wrapper

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37345>
 2025-09-19 21:08:25 -04:00
Georg Lehmann 14dfc05f83 radv: use rt wave size in fragment shaders with ray queries 
Usually wave64 performs better for fragment shaders,
because LDS sharing for interpolation is better.

But the rt traversal loop divergence is likely high enough to make
wave32 better on GFX10.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37360>
 2025-09-19 11:06:06 +00:00
Georg Lehmann 4a080a8904 radv: allow application required fragment shader subgroup size 
If the application really thinks it needs pswave32, let it use it.
Fragment shaders also have no concept of full subgroups, so the existing
code that chooses the subgroup size will work already.

For pre raster stages, we cannot allow this because of potential mismatches
in merged stages.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37360>
 2025-09-19 11:06:06 +00:00
Hans-Kristian Arntzen 3bc81ee6f1 radv/sqtt: Ensure that present fence gets signalled. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 88cbe32048 ("radv: add support for RGP queue events")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37438>
 2025-09-18 14:58:39 +00:00
Rhys Perry d6ed68212c aco: fix SGPR 8-bit nir_op_vec with mixed constant and non-constant 
For example, vec2(non_const, const)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 04e3d7ad93 ("aco: improve nir_op_vec with constant operands")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13911
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37405>
 2025-09-18 12:37:19 +00:00
Eric Engestrom f2c4c5493e radv: add comment explaining why fp16 is disabled by default on gfx8 
Suggested-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37442>
 2025-09-18 09:08:21 +00:00
Eric Engestrom 1ee1e63bdb radv: make sure fp16 is enabled consistently on gfx8 
Fixes `dEQP-VK.api.info.vulkan1p4_limits_validation.general`

Fixes: f0f4ae1713 ("radv: Add radv_enable_float16_gfx8 drirc and enable for Indiana Jones TGC")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37442>
 2025-09-18 09:08:21 +00:00
Rhys Perry 8931672eef aco: workaround load tearing for load_shared2_amd 
This probably has the same issue as load_shared.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 04956d54ce ("aco: force uniform result for LDS load with uniform address if it can be non uniform")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Rhys Perry 81df517553 aco: avoid unaligned offsets when selecting load_global_amd 
SMEM instructions mask off the low bits for the base and offset sources
both before and after they're added. However, NIR expects ACO to only
care about the alignment of the final address.

fossil-db (gfx1201):
Totals from 21 (0.03% of 79839) affected shaders:
Instrs: 229780 -> 229876 (+0.04%)
CodeSize: 1267724 -> 1268080 (+0.03%)
Latency: 2800924 -> 2800978 (+0.00%)
InvThroughput: 520250 -> 520256 (+0.00%)
Copies: 27878 -> 27876 (-0.01%); split: -0.01%, +0.00%
SALU: 29591 -> 29643 (+0.18%)

fossil-db (polaris10):
Totals from 3 (0.00% of 62201) affected shaders:
Latency: 2651 -> 2652 (+0.04%)
InvThroughput: 662 -> 663 (+0.15%)
PreSGPRs: 51 -> 54 (+5.88%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37301>
 2025-09-17 09:15:46 +00:00
Rhys Perry 6d71521ecd aco: avoid wraparound for smem global loads with both offsets 
fossil-db (gfx1201):
Totals from 296 (0.37% of 79839) affected shaders:
Instrs: 382593 -> 380149 (-0.64%)
CodeSize: 1981452 -> 1970988 (-0.53%); split: -0.53%, +0.00%
Latency: 1575286 -> 1574252 (-0.07%)
InvThroughput: 215839 -> 215818 (-0.01%)
SClause: 8679 -> 8677 (-0.02%); split: -0.03%, +0.01%
Copies: 19642 -> 19641 (-0.01%); split: -0.03%, +0.02%
PreSGPRs: 14521 -> 14515 (-0.04%)
SALU: 57097 -> 55718 (-2.42%)

fossil-db (polaris10):
Totals from 30 (0.05% of 62201) affected shaders:
Instrs: 23341 -> 23379 (+0.16%); split: -0.01%, +0.18%
CodeSize: 121316 -> 121516 (+0.16%); split: -0.01%, +0.17%
SGPRs: 2368 -> 2384 (+0.68%)
Latency: 235153 -> 235374 (+0.09%); split: -0.01%, +0.11%
InvThroughput: 92582 -> 92566 (-0.02%)
SClause: 616 -> 619 (+0.49%)
Copies: 2717 -> 2720 (+0.11%)
PreSGPRs: 1204 -> 1213 (+0.75%)
SALU: 3654 -> 3692 (+1.04%); split: -0.08%, +1.12%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.2
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37301>
 2025-09-17 09:15:46 +00:00
Konstantin Seurer ea51a67996 vulkan/bvh: Enable glsl extensions in meson 
Having a list of all enabled/used extensions in meson allows us to get
rid of a lot of boilerplate in every bvh build shader.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35326>
 2025-09-16 20:18:01 +00:00
Georg Lehmann 714a149396 nir: remove unsigned upper bound config 
All config information is now either in nir->info or nir->options.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37361>
 2025-09-16 09:24:04 +00:00
Georg Lehmann bb67dae12d nir/uub: remove max_workgroup_size from config 
For most hardware, this is the same as max invocations in the workgroup.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37361>
 2025-09-16 09:24:04 +00:00
Georg Lehmann f3c08c9d27 nir/uub: use shader_info subgroup size 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37361>
 2025-09-16 09:24:04 +00:00
Georg Lehmann d029686e20 aco/isel: fix output args init stack buffer overflow 
BITSET range functions include the end of the range.

Fixes: eb249bb18e ("aco: Only fix used variables to registers")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37361>
 2025-09-16 09:24:03 +00:00
nihui 849344dc08 aco: set program->dev.fused_mad_mix=true for GFX940 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35655>
 2025-09-16 07:02:32 +00:00
nihui 8c4f0b1353 aco: gfx940 has no mad f32 instruction 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35655>
 2025-09-16 07:02:32 +00:00
Valentine Burley 8803388d15 ci: Update to Debian 13 (trixie) 
Switch containers from Debian 12 (bookworm) to Debian 13 (trixie).

Trixie ships LLVM 19 by default, so we no longer need to add LLVM repos
to install llvm-19.

Notably, trixie also uses Python 3.13.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6994
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35853>
 2025-09-16 06:16:21 +00:00
Valentine Burley b16c62b6b2 meson: Relax -Wmaybe-uninitialized errors 
Suggested-by: @eric

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35853>
 2025-09-16 06:16:20 +00:00
Samuel Pitoiset 0bc0ead674 radv: set DRLR mapping info from inheritance info when present 
These two structs are allowed to be in pNext and they should match
the primary command buffer info.

Found while implementing a new extension.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37278>
 2025-09-15 19:29:34 +00:00
Samuel Pitoiset 5907dbfc09 radv: remove redundant RADV_DYNAMIC_RASTERIZATION_SAMPLES 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:42 +00:00
Samuel Pitoiset 2084cb59f2 radv: remove redundant RADV_DYNAMIC_POLYGON_MODE 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:42 +00:00
Samuel Pitoiset c1a1aed665 radv: remove redundant RADV_DYNAMIC_LINE_RASTERIZATION_MODE 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:41 +00:00
Samuel Pitoiset d8bc573ee9 radv: remove redundant RADV_DYNAMIC_PRIMITIVE_TOPOLOGY 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:40 +00:00
Samuel Pitoiset 43d7795274 radv: pre-compute vgt_outprim_type 
This will allow us to optimize the number of states to emit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:39 +00:00
Samuel Pitoiset c8245173a0 radv: pre-compute the line rasterization mode 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:39 +00:00
Samuel Pitoiset 469350328c radv: pre-compute the number of rasterization samples 
The number of rasterization samples depend on many various states.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36988>
 2025-09-15 19:10:38 +00:00
Samuel Pitoiset 8d991c2572 radv/meta: remove useless assertion when choosing resolve method 
The destination image layout is used for depth/stencil resolves and
asserting isn't very useful.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:55 +00:00
Samuel Pitoiset c8f6b27964 radv/meta: simplify calling depth/stencil resolve helpers 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:55 +00:00
Samuel Pitoiset 39725fc935 radv/meta: simplify barriers for resolves 
This is equivalent.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:54 +00:00
Samuel Pitoiset e673ccfcb5 radv/meta: remove useless VK_ACCESS_2_SHADER_WRITE_BIT for subpass resolves 
This doesn't do anything.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:54 +00:00
Samuel Pitoiset 704fbbb108 radv/meta: rework depth/stencil resolves using graphics 
This adds a new helper that doesn't depend on the rendering info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:53 +00:00
Samuel Pitoiset 141beaee4e radv/meta: rework depth/stencil resolves using compute 
This adds a new helper that doesn't depend on the rendering info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:53 +00:00
Samuel Pitoiset 2207d1e732 radv/meta: fix saving push constants for depth/stensil resolves on compute 
Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37300>
 2025-09-15 18:52:52 +00:00
Natalie Vock e3460f15fa aco/opt: Work around GCC compiler issue 
No functional change. Random code churn that, apparently, makes a
GCC miscompile disappear.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34531>
 2025-09-15 17:16:21 +00:00