AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
169,234 Commits 1 Branch 0 Tags
7fe469d6c809eaacbdb5a04bdcd8a5b0d7fc557b
Commit Graph

169234 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Tatsuyuki Ishi
7fe469d6c8 radv: Pre-compute descriptor set layout hash. 
While analyzing cache loading performance, hashing the pipeline layout was
surprisingly consuming around 4% of time, sometimes close to the cost of
hashing shader modules.

Turns out we were hashing the pipeline layout on every pipeline creation.
Considering that pipeline layouts are usually deduplicated by the
application, this was amplifying the hashing cost by a big margin.

With Graphics Pipeline Library, we do need to rebuild the pipeline layout
by combining those from each library, but we can memoize the hash of the
descriptor set layout. The cost of re-hashing hashes is negligible since
each descriptor set layout can amount to 1–2KB in size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22254>
 2023-04-03 08:46:08 +00:00
Nataraj Deshpande
71fe9dfe07 anv: Bump VkDeviceMemory objects limit to 4GB 
Android CTS 13_r4 tests dEQP-VK.memory.allocation.random* fail
with VK_ERROR_OUT_OF_DEVICE_MEMORY on ADL boards with 32GB memory
as memory allocation requests from DEQP are much larger(~2.9GB+)
based on device heap size/8.

Increase the limit to unsigned 32bit max(~4GB) which helps to
fix the dEQP-VK.memory.allocation.random* tests.

v1: Bound allocation by the largest memory heap size (Lionel Landwerlin)

v2: Clean up comments to reflect the code change (Ivan Briano)
    Update the value of MAX_MEMORY_ALLOCATION_SIZE (Lionel Landwerlin)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22066>
 2023-04-03 06:18:52 +00:00
Lionel Landwerlin
b7e5b3e318 isl: update max buffer size for SKL+ 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22066>
 2023-04-03 06:18:52 +00:00
Lionel Landwerlin
00fc927e52 anv: take care of maxStorageBufferRange being uint32_t 
Not fixing anything, but required for another fix.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22066>
 2023-04-03 06:18:52 +00:00
Qiang Yu
7be81a680b ac/llvm: remove ac_build_opencoded_load_format 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu
1165758b8b ac/llvm,radeonsi: remove abi->load_inputs implementation 
No nir_load_input in VS now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu
894d92995c radeonsi: monolithic VS emit prolog in nir directly 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu
531acf548a ac/llvm: move ac_fixup_ls_hs_input_vgprs to amd common 
To be shared with radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu
297f97a42b ac/llvm: vs_rel_patch_id can also be fixed up 
It's currently used when LS store output to LDS.
The LS/HS bug fix seems does not affect this case.
But we'd better treat it as other fixed args.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu
7ab7eccddd radeonsi: add si_nir_lower_vs_inputs 
Ported from llvm:
* si_load_vs_input
* ac_build_opencoded_load_format
* ac_ufN_to_float
* get_vertex_index
* ac_build_fast_udiv_nuw

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu
003d84b660 ac/nir: add ac_nir_load_arg_at_offset 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Qiang Yu
e6f69853be radeonsi: expose si_nir_load_internal_binding 
PS polygon stippling is going to use it too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22045>
 2023-04-03 01:35:06 +00:00
Mauro Rossi
b40e7dcf82 hasvk: include "vk_android.h" header in anv_android.c 
Fixes the following building errors:

../src/intel/vulkan_hasvk/anv_android.c:387:34: error: implicit declaration of function 'vk_alloc_ahardware_buffer' is invalid in C99 [-Werror,-
Wimplicit-function-declaration]
   struct AHardwareBuffer *ahw = vk_alloc_ahardware_buffer(pAllocateInfo);
                                 ^
../src/intel/vulkan_hasvk/anv_android.c:387:28: error: incompatible integer to pointer conversion initializing 'struct AHardwareBuffer *' with an expression of type 'int' [-Werror,-Wint-conversion]
   struct AHardwareBuffer *ahw = vk_alloc_ahardware_buffer(pAllocateInfo);
                           ^     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2 errors generated.

Fixes: b16cfe23 ("vulkan,anv,hasvk,radv: Unify Android hardware buffer creation")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22251>
 2023-04-02 23:30:42 +02:00
Timur Kristóf
4de9a4b2b8 ac/nir: When task->mesh dispatch Y or Z are 0, also set X to 0. 
AMD recommends doing this to speed up the CP when it processes
the draw ring entries. LLPC also does this.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211>
 2023-04-01 14:46:50 +00:00
Timur Kristóf
4683b21399 ac/nir: Store only lowest 8 bits for task draw ring DWORD3. 
When writing the draw ready bit, don't write the high 24 bits
of DWORD3, because that is used by the HW for something else
according to LLPC.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211>
 2023-04-01 14:46:50 +00:00
Rhys Perry
6974e5479c aco: fix nir_var_shader_out barriers for task shaders 
These will be used in a future commit.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22211>
 2023-04-01 14:46:50 +00:00
Rob Clark
d698bf0523 freedreno: Support the disable_throttling=true driconf option 
At this point, mostly just to make it easier to disable throttling for
performance debugging.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Rob Clark
77a5778836 freedreno: Move driconf settings into sub-struct 
Organize all one of them in a single place before adding more.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Rob Clark
8620b64930 freedreno: Avoid looping shader stages if nothing dirty 
We have corresponding global dirty bits for each of the per-stage dirty
bits.  We can use this to skip iterating over shader stages when there
is no per-stage dirty state to handle.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Rob Clark
0a62a874fc freedreno: Re-work dirty-resource tracking 
If a resource is dirty but already tracked by the current batch, no need
to process it at draw time.

Note that the batch could change (ie. new fb state bound, etc) after the
check if we need resource dirty tracking, but in these cases all the
dirty-resource state is marked dirty.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Rob Clark
4c0fdef42c freedreno: Inline single-use helpers 
bind_sampler_states() / set_sampler_views() have just a single caller.
So inline them.  Needed for next commit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Rob Clark
7099f628c5 freedreno: Extract out a helper 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Rob Clark
0408ddcda9 freedreno: Hoist dirty vars 
Prep to re-work how we track dirty-resource.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Rob Clark
19a138adcf freedreno: Stop being too clever by half 
This wasn't taking into account a change in corresponding bit in
writeable_bitmask, causing problem if an SSBO was first bound for
read, and then rebound for write, we wouldn't update the buffers
valid range.  Instead just drop the premature optimization.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Connor Abbott
b123ee707d freedreno: Fix or/and'ing two BitmaskEnums 
Previously when there was an & or | with two BitmaskEnums, the compiler
would try to cast the RHS and find a matching overload, but there were
many different casts (to the enum itself, to an integer, to a boolean,
etc.) each with a matching overload which meant that it couldn't pick
one and errored out due to an ambiguous overload. Fix this by
explicitly providing an overload that takes a BitmaskEnum on the RHS.
It has to also provide a BitmaskEnum output, so that subsequent
operators with the result on the LHS (e.g. when or'ing together three
BitmaskEnums without any parentheses tricks) also get the right
overload.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22224>
 2023-04-01 13:53:31 +00:00
Pavel Ondračka
5825f9dd68 nine: use separate register for aL emulation 
NIR loop unrolling is only working if the loop counter is a scalar.
So keep the loop counter separate and move the aL emulation and
the aL increment to a new register.

This allows loop unrolling with vec4 backends where unconditional
scalarizing of phi nodes is undesirable, like for example r300.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7222
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21243>
 2023-04-01 11:12:55 +00:00
Karol Herbst
ac993ae828 rusticl/kernel: make use of cso info 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
c7dd3677dc panfrost: implement get_compute_state_info 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
87aeea20ac panfrost: move max_thread_count and take reg_count into account 
We'll need it to report proper thread counts for OpenCL.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
3212ac4658 nvc0: implement get_compute_state_info 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
52f03f63e7 nv50: implement get_compute_state_info 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
c1c0362d34 iris: implement get_compute_state_info 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
5fa297dadd lp: implement get_compute_state_info 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
6305d1cb1c gallium: add get_compute_state_info 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
87147e2b09 rusticl/kernel: set has_variable_shared_mem on the nir 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Karol Herbst
0e5722cd22 nir: track existence of variable shared memory 
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19855>
 2023-03-31 20:29:00 +00:00
Sil Vilerino
1995762d68 Revert "d3d12: Honor suggested driver profile/level for H264/HEVC encode" 
This reverts commit 37652da616.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22239>
 2023-03-31 20:13:20 +00:00
Rhys Perry
0f60c18f29 aco: don't optimize s_or_b64(v_cmp_u_f32(a, b), cmp(a, a)) 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22214>
 2023-03-31 19:41:54 +00:00
Charlie Birks
46e7a127d9 docs: add a few vulkan extensions supported by multiple drivers 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11445>
 2023-03-31 19:35:36 +00:00
Konstantin Seurer
7b837531e8 radv/ci: Update ray tracing pipeline fail/skip lists 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22018>
 2023-03-31 19:05:17 +00:00
Samuel Pitoiset
e98aded527 radv: fix binding raytracing/compute pipelines 
If a compute pipeline is bound after a raytracing pipeline, the
computes shader slot (aka RT prolog) will be overwritten.

To fix this, move the RT prolog outside of the compute shader slot.

Fixes: d109362a3d ("radv: copy bound shaders to the cmdbuf state")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22235>
 2023-03-31 18:29:05 +00:00
Samuel Pitoiset
56493a5f8a radv: add the raygen shader BO to the cmdbuf list 
Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22235>
 2023-03-31 18:29:05 +00:00
Timur Kristóf
115958b6f0 ac/nir/ngg: Slightly improve attribute ring offset calculation. 
Inspired by Nicolai Hähnle's commit in LLPC.
Instead of using a SALU instruction to add to the scalar
offset, rely on the buffer swizzling and use constant offset.

Fossil DB stats on GFX1100:

Totals from 47910 (35.51% of 134913) affected shaders:
CodeSize: 87927612 -> 86968136 (-1.09%)
Instrs: 17584007 -> 17440094 (-0.82%)
Latency: 97232173 -> 97126311 (-0.11%)
InvThroughput: 9904586 -> 9905288 (+0.01%); split: -0.02%, +0.02%
VClause: 544430 -> 542566 (-0.34%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22227>
 2023-03-31 17:02:17 +00:00
Timur Kristóf
61003e3600 radv: Use radv_get_shader to get vertex shader when binding pipeline. 
The shaders[MESA_SHADER_VERTEX] can be NULL for merged shaders.

Fixes: b2ac40e734
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8749
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22229>
 2023-03-31 16:42:39 +00:00
Samuel Pitoiset
f8558d1fb5 radv: configure PA_SC_MODE_CNTL_1 during cmdbuf recording 
Two graphics pipeline parameters need to be copied to the cmdbuf
state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22218>
 2023-03-31 16:07:11 +00:00
Samuel Pitoiset
66da73e863 radv: set PS_ITER_SAMPLE(1) for sample shading during cmdbuf recording 
This shouldn't be configured in the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22218>
 2023-03-31 16:07:11 +00:00
Samuel Pitoiset
b750fe4c6a radv: copy db_render_control to the cmdbuf state 
This register is only used for meta operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22218>
 2023-03-31 16:07:11 +00:00
José Roberto de Souza
e6c9b6eddc iris: Implement Xe version of bo_madvise() and bo_set_caching() 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22060>
 2023-03-31 15:40:27 +00:00
Maarten Lankhorst
c10ff19704 iris: Place scanout buffers only into lmem for discrete GPUs 
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22060>
 2023-03-31 15:40:27 +00:00
José Roberto de Souza
d72705ce43 iris: Handle allocation of scanout buffers in Xe 
Bos that will be scanout in display need to be allocated with
flags = XE_GEM_CREATE_FLAG_SCANOUT in Xe and that implies to different
caching rules for this buffer.

So here not allowing to get scanout buffer from cache or allow it
to be placed in a cache bucket for reuse.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22060>
 2023-03-31 15:40:27 +00:00