91798bab2d
anv: refactor emit_dynamic_buffer_binding_table_entry
...
Refactor emit_dynamic_buffer_binding_table_entry to emit a null surface
state when the descriptor has no assocaited buffers allowing us to drop
the same check elsewhere.
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27005 >
2024-01-12 11:55:41 +00:00
695b4a2992
anv: fix disabled Wa_14017076903/18022508906
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: d0669f3edejose.souza@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27008 >
2024-01-11 23:36:05 +00:00
62c21c240e
anv: remove ANV_ENABLE_GENERATED_INDIRECT_DRAWS variable
...
We have a threshold drirc value & environment variable.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26967 >
2024-01-10 18:32:24 +00:00
29fc135a55
anv: use workaround framework for Wa_22018402687
...
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26925 >
2024-01-10 08:26:41 +00:00
ad158b0bee
anv: Call anv_measure_submit() before anv_cmd_buffer_chain_command_buffers()
...
Otherwise the measurement instructions will be placed after the
MI_BATCH_BUFFER_START calling the next cmd_buffer.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:19 +00:00
d37414d8a4
anv: Fix anv_measure_start/stop_snapshot() over copy or video engine
...
Those engines don't have PIPE_CONTROL so we can't do
ANV_TIMESTAMP_CAPTURE_AT_CS_STALL but we can support measurement
by changing the capture type to ANV_TIMESTAMP_CAPTURE_TOP/END_OF_PIPE
Right now this issue is only reproduced in Xe KMD without setting
any special parameters(other than INTEL_MEASURE) because Xe KMD allows
the usage of copy engine while i915 can't due TRTT restrictions.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:19 +00:00
b8d48ebc93
anv: Add missing anv_measure_submit() calls in Xe KMD backend
...
Without this intel_measure don't work with Xe KMD.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:19 +00:00
a0f7820fe8
anv: Simply companion_rcs handling
...
Here dropping is_companion_rcs_cmd_buffer parameter of a few functions
that don't need this information, it just need the right
anv_cmd_buffer for each case.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:18 +00:00
428a179865
anv: Drop useless STATIC_ASSERT in anv_physical_device_init_queue_families()
...
assert(family_count <= ANV_MAX_QUEUE_FAMILIES) already takes care
of STATIC_ASSERT without need of updates.
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:18 +00:00
0997766069
anv: Increase ANV_MAX_QUEUE_FAMILIES
...
If ANV_VIDEO_DECODE, ANV_VIDEO_DECODE and INTEL_COPY_CLASS are enabled
it is possible to have 5 different queues, so here increasing
ANV_MAX_QUEUE_FAMILIES.
Fixes: 17b8b2cffdjose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26882 >
2024-01-09 14:28:18 +00:00
c21213b438
anv: Don't print warnings for GRL kernel compilations
...
Make the build less chatty. The current warnings are about certain
capabilities not being fully supported, which we don't care for these
particular kernels.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26939 >
2024-01-09 01:26:41 +00:00
a6a95591aa
intel/dev: poison macros for workarounds fixed at a stepping
...
INTEL_NEEDS_WA macros are valid when a workaround applies to all
platforms which have the GFX_VERx10 versions for the workaround.
Some workarounds were fixed at a stepping after the platform release.
If a workaround applies partially to any platform, then GFX_VERx10
cannot be used to correctly apply the workaround.
This change invalidates INTEL_NEEDS_WA_16014538804 and
INTEL_NEEDS_WA_22014412737, which were fixed for MTL platforms at
stepping b0. The run-time checks were already present for all uses of
these macros. Updating the poisoned macros to INTEL_WA_{num}_GFX_VER
compiles out the run-time checks on platforms where they cannot apply.
Acked-by: Caio Oliveira <caio.oliveira@intel.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898 >
2024-01-05 22:51:45 +00:00
d6c258d9ee
util: Add align_uintptr and use it treewide to replace ALIGN that works on size_t and uintptr_t
...
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Acked-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26866 >
2024-01-05 21:54:35 +00:00
472b6f5379
intel,crocus,iris: Use align64 instead of ALIGN for 64 bit value parameter
...
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864 >
2024-01-03 12:46:10 +00:00
188c349e51
intel: remove workaround for preproduction DG2 steppings
...
DG2_G10 was released with stepping C0.
DG2_G11 was released with stepping B1.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26845 >
2024-01-02 16:06:37 -08:00
56d556f821
anv: enable VK_KHR_maintenance6
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842 >
2024-01-02 22:12:02 +00:00
b7c4fe54cb
anv: move astc_emu to use descriptors2 calls
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842 >
2024-01-02 22:12:02 +00:00
ce6899d804
anv: add support for Cmd*DescriptorSet*2KHR
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842 >
2024-01-02 22:12:02 +00:00
40377eed91
anv: handle VkBindMemoryStatusKHR on buffer/image memory bind
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842 >
2024-01-02 22:12:02 +00:00
abe0cc8aa4
anv: remove no longer valid assert
...
Maintenance6 allows creating uncompressed views of compressed images
with multiple layers.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842 >
2024-01-02 22:12:02 +00:00
3b5615500a
anv: allow NULL index buffers
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26842 >
2024-01-02 22:12:01 +00:00
9e97ce59a8
anv: No need to emit PIPELINE_SELECT on Xe2+
...
On Xe2+, PIPELINE_SELECT is getting deprecated (Bspec 55860), as a
result we don't have to do the stalling flushes while switching between
different pipelines.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26637 >
2024-01-02 20:57:33 +00:00
8ea032b78e
intel/dev: Advertise integer configs with saturatingAccumulation too
...
VUID-RuntimeSpirv-saturatingAccumulation-08983 says:
For OpCooperativeMatrixMulAddKHR, the SaturatingAccumulation
cooperative matrix operand must be present if and only if
VkCooperativeMatrixPropertiesKHR::saturatingAccumulation is VK_TRUE.
As a result, we have to advertise integer configs both with and without
this flag set.
v2: Prefix type names with INTEL_CMAT_. Suggested by Lionel.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
f952dd510e
anv: Select the SIMD mode very early when cooperative matrices are used
...
The commit is a little ugly. The definition of anv_fixup_subgroup_size
is moved before the added call site. In addition, the bit starting at
the "Cooperative matrix extension requires..." comment is added.
v2: Dramatic simplification of SIMD selection. Suggested by Caio.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
511f91e307
anv: Lower indirect derefs again after lowering cooperative matrices
...
The cooperative matrix lowering can generate a lot of indirect array
accesses, and these need to be eliminated.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
b741a9a851
anv: Set PIPELINE_SELECT systolic mode enable flag
...
Set the flag on compute shaders when the application has enabled the
cooperative matrix feature. We might still want to enable this only when
DPAS is actually used. The current method is based on many suggestions
from Lionel.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
7bfbeb79a7
anv: Set COMPUTE_WALKER systolic mode enable flag
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
67739b02de
anv: Add anv_physical_device::has_cooperative_matrix
...
This flag tracks whether or not cooperative matrices are fully enabled
on the physica device (i.e., both the configs exist and the environment
varible is set). This is mainly to support a later commit "anv: Set
PIPELINE_SELECT systolic mode enable flag."
This could be squashed into "anv: Implement VK_KHR_cooperative_matrix."
I left it separate because we might go back to the previous method.
v3: Don't hide the extension behind an environment variable
(ANV_COOPERATIVE_MATRIX) now the we have a better solution for setting
PIPELINE_SELECT.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
0a6f8b40bf
anv: Implement VK_KHR_cooperative_matrix
...
v2: Rebase on moving lowering pass to src/intel/compiler.
v3: Don't hide the extension behind an environment variable
(ANV_COOPERATIVE_MATRIX) now the we have a better solution for setting
PIPELINE_SELECT.
v4: Prefix type names with INTEL_CMAT_. Suggested by Lionel. Also rebase
on f99e43d606ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
3465e9f352
anv: Assume that imported bos already have flat CCS requirements satisfied
...
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26711 >
2023-12-27 18:05:04 +00:00
8d0e70f628
anv: Replace anv_bo.vram_only by anv_bo.alloc_flags check
...
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26711 >
2023-12-27 18:05:04 +00:00
060439bdf0
anv: Add ANV_BO_ALLOC_IMPORTED
...
The next patch will replace anv_bo.is_vram by a anv_bo.alloc_flags
check but to that actually work we can't use ANV_BO_ALLOC_NO_LOCAL_MEM
for imported bos, so here adding it.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10291
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26711 >
2023-12-27 18:05:04 +00:00
69cc72e50a
anv/gfx12: Hook up dual-SIMD8 fragment shader dispatch.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
1eff2fcb62
intel/compiler: Add polygon count statistic to brw_compile_stats.
...
And use it in ANV in order to return a "SIMDNxM" name from
vkGetPipelineExecutablePropertiesKHR.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:30 +00:00
e7b1993376
intel/compiler: Add max_polygons FS compilation parameter.
...
Add a brw_compile_fs_params parameter that specifies to the compiler
the maximum number of polygons that may be processed in parallel per
PS SIMD thread.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:30 +00:00
ed45f95b51
intel/vulkan: Add COMPRESSED_CLEAR state in layout translation
...
The added state is for RC_CCS_CC modifiers that support fast
clear.
Fix:
vkcube: ../src/intel/vulkan/anv_image.c:2686: anv_layout_to_aux_state:
Assertion `!"" "unexpected isl_aux_state"' failed.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
24b4f9c3ba
intel/vulkan: Update comment of a workaround of modifiers
...
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
12f0715787
intel/vulkan: Correct a comment about an offset in fast clear
...
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
9c5a28d919
intel/vulkan: Use the last 2 dwords of clear color struct
...
Refer to the comments added in the code, we now take the
last 2 dwords in the clear color struct to store the fast
clear type and the first compression state.
Suggested by Nanley Chery <nanley.g.chery@intel.com >
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
82f47acb16
intel/vulkan: Remove private binding on fast clear region
...
To support modifiers with fast clear color, the region
should be able to export along with main surface, so we
remove the private binding in such case.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
91a10251b9
intel/vulkan: Import aux state tracking buffer
...
Pass down the offset of aux state tracking buffer
of an imported image from the layout provided from
the application.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
1d5326b30e
intel/vulkan: Specify offset when creating aux state tracker
...
Allow aux state tracking buffer created with different offsets,
in order to support importing images with drm modifiers. We
will always need to calculate the size of an imported fast
clear region because Vulkan spec defines:
VUID-VkImageDrmFormatModifierExplicitCreateInfoEXT-size-02267
For each element of pPlaneLayouts, size must be 0
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
a26d62df6b
intel/vulkan: Allow modifiers supporting fast clear
...
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
ab6f1b1d57
intel/vulkan: Report clear color in subresource layout
...
To support drm modifiers with fast clear features, this
change reports the layout of the region back to application.
Because it tracks all levels and layers in that plane, the
whole region is reported back regardless the level and
layer are being queried.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Acked-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651 >
2023-12-19 13:57:16 +00:00
30faa7a483
anv, iris, intel/genxml: Update 3DSTATE_HS for xe2
...
Update 3DSTATE_HS programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
8ba9988858
anv, iris, intel/genxml: Update 3DSTATE_GS for xe2
...
Update 3DSTATE_GS programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
a659b1f0c0
anv, blorp, iris, intel/genxml: Update 3DSTATE_PS_EXTRA for xe2
...
Update 3DSTATE_PS_EXTRA programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
5548e6a478
anv, blorp, iris, intel/genxml: Update 3DSTATE_VS for xe2
...
Update 3DSTATE_VS programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
f170995e66
anv, blorp, iris: Update 3DSTATE_PS programming for xe2
...
Rework:
* Jordan: Move code into intel_update_ps_state()
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:30 +00:00
ba6faeb974
anv: Remove libdrm usage from Xe KMD backend
...
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26699 >
2023-12-15 20:40:49 +00:00
Rohan Garg