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Author SHA1 Message Date
Marek Olšák 7bf5d2ce75 radeonsi: add assertion requiring binding vertex elements before vertex_buffers 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák 1638d486ff gallium/u_threaded,st/mesa: add a merged set_vertex_elements_and_buffers call 
Setting vertex elements before vertex buffers is a new requirement of gallium.

This is the only way to set the vertex elements state after vertex buffers
in st/mesa while setting the state before vertex buffers in tc_batch_execute.

A new TC call is added to set both vertex elements and vertex buffers.
Vertex buffers are filled by st/mesa first, and then the vertex elements
state is set in the same call. When TC calls it, it binds vertex elements
before vertex buffers.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák 2606ceacdd cso_context: add cso_get_vertex_elements_for_bind, letting the caller bind it 
for st/mesa

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák 58b3d24b25 nine: bind exactly the number of vertex buffers as vertex elements need 
gallium will require this (radeonsi won't work otherwise).

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák 05fa8391b9 nine: remove unused last_vtxbuf_count 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák ecbbbae5c3 nine: always update vertex buffers after updating vertex elements 
gallium will require this. (radeonsi won't work otherwise)

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Marek Olšák 36d8191176 nine: change the vtxbuf dirty mask to bool 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27736>
 2025-02-25 09:24:25 +00:00
Samuel Pitoiset c64b8c8401 radv: stop computing the UUID using the physical device cache key 
Otherwise, the UUID changes for games that have shader-based drirc
workarounds and this breaks precompiled shaders on SteamDeck.

Instead, use this pdev cache key to compute the logical device hash
which is common to all pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33717>
 2025-02-25 07:59:02 +00:00
Peyton Lee 4fe586f71e radeonsi/vpe: support geometric scaling 
When the reduction ratio exceeds the hardware limit,
enable the geometric scaling mechanism.

Signed-off-by: Peyton Lee <peytolee@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33528>
 2025-02-25 07:29:46 +00:00
Peyton Lee e85a6b6a63 radeonsi/vpe: check reduction ratio 
Check the reduction ratio is within the hardware capablity.

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33528>
 2025-02-25 07:29:46 +00:00
Faith Ekstrand c9ba28da55 nak/nir: Don't provide dummy backend2 tex srcs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33716>
 2025-02-25 01:43:22 +00:00
Faith Ekstrand ff0a82e785 nak: Handle tex ops with only one source 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33716>
 2025-02-25 01:43:22 +00:00
Faith Ekstrand 58218c7349 nvk: Do not set INVALIDATE_SKED_CACHES pre-MaxwellB 
The other two uses of this are behind guards but we forgot this one.

Fixes: 976f22a5da ("nvk: Implement CmdProcess/ExecuteGeneratedCommandsEXT")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33716>
 2025-02-25 01:43:22 +00:00
Faith Ekstrand c145147871 nvk: Don't bind a fragment shading rate image pre-Turing 
Fixes: 75bcb656d9 ("nvk: Add support for binding fragment shading rate images")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33716>
 2025-02-25 01:43:22 +00:00
Faith Ekstrand f441ed1f7b nvk/nvkmd: Fix logging of VA bind addresses 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33716>
 2025-02-25 01:43:22 +00:00
Timothy Arceri 5ad508d743 util/disk_cache: dont create multidisk cache dir if unused 
As reported in issue #11825 the code that is meant to clean up old
cache dirs actually ends up creating an empty dir due to reusing
existing code to create the cache path required for the potential
cleanup.

Here we make the code more flexible allowing cache path strings
to be returned by the helpers if the directory already exists
or returning NULL if we don't want to create a new directory.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11825
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33699>
 2025-02-25 00:11:03 +00:00
Lorenzo Rossi 4d36528d04 nak: Fold bool-int-bool conversions 
As explained in https://gitlab.freedesktop.org/mesa/mesa/-/issues/10204
there are places in the NAK backend where we emit i2b(b2i(x))
conversions that cannot be folded by NIR passes.

This commit adds to the copy propagation pass the ability to track
boolean conversions, folding them whenever possible.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10204
Signed-off-by: Lorenzo Rossi <snowycoder@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33646>
 2025-02-24 23:50:52 +00:00
Caio Oliveira 7311bcfd6a intel/brw: Don't need to repair CFG in brw_opt_combine_constants 
Since a previous change ensured that a DO-block is guaranteed to not be
followed by a DO-block, it is sufficient to pick the next block without
requiring to repair the CFG.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33536>
 2025-02-24 23:25:06 +00:00
Caio Oliveira d2c39b1779 intel/brw: Always have a (non-DO) block after a DO in the CFG 
Make the "block after DO" more stable so that adding instructions after
a DO doesn't require repairing the CFG.  Use a new SHADER_OPCODE_FLOW
instruction that is a placeholder representing "go to the next block"
and disappears at code generation.

For some context, there are a few facts about how CFG currently works

- Blocks are assumed to not be empty;
- DO is always by itself in a block, i.e. starts and ends a block;
- There are no empty blocks;
- Predicated WHILE and CONTINUE will link to the "block after DO";
- When nesting loops, it is possible that the "block after DO" is
  another "DO".

Reasons and further explanations for those are in the brw_cfg.c comments.

What makes this new change useful is that a pass might want to add
instructions between two DO instructions.  When that happens, a new
block must be created and any predicated WHILE and CONTINUE must be
repaired.

So, instead of requiring a repair (which has proven to be tricky in
the past), this change adds a block that can be "virtually" empty but
allow instructions to be added without further changes.

One alternative design would be allowing empty blocks, that would be
a deeper change since the blocks are currently assumed to be not empty
in various places.  We'll save that for when other changes are made to
the CFG.

The problem described happens in brw_opt_combine_constants, and a
different patch will clean that up.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33536>
 2025-02-24 23:25:06 +00:00
Caio Oliveira d32a5ab0e4 intel/brw: Use the builder DO() function in all places 
Shorter and a preparation to add some functionality to DO().

Had to make it const since that's the convention for builder, so
just made all the sibling helpers const too.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33536>
 2025-02-24 23:25:06 +00:00
Stéphane Cerveau 5f8f3db475 anv: fix error code in GetPhysicalDeviceVideoFormatProperties 
If no video profile format found, we should return
the custom error code
VK_ERROR_VIDEO_PROFILE_FORMAT_NOT_SUPPORTED_KHR.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33709>
 2025-02-24 23:03:43 +00:00
Natalie Vock 14b902c825 radv/rt: Don't allocate the traversal shader in a capture/replay range 
We never write the traversal shader address out to shader group handles,
so this is not necessary. On the flipside, it can cause conflicts if the
traversal shader is allocated in a range occupied by a replayed shader.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33711>
 2025-02-24 22:41:19 +00:00
Alyssa Rosenzweig feedd427b3 nvk: rewrite query copy shader in CL C 
as previously discussed.

this is using "library CL" instead of kernel CL, which is the older way of doing
things. it works, it just has more boilerplate per-kernel than we'd want
otherwise. but library CL is basically free to integrate into a driver, whereas
kernel CL requires a lot more upfront investment. (I'm working on cleaning that
up but we're not quite there yet.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33362>
 2025-02-24 21:15:26 +00:00
Georg Lehmann c249556bf4 aco/insert_exec: fix continue_or_break on gfx6-7 
s_cmp_lg_u64 is gfx8+

Fixes: 115ff5f95b ("aco/insert_exec_mask: don't restore exec in continue_or_break blocks")

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33715>
 2025-02-24 20:41:17 +00:00
Alyssa Rosenzweig 904760ff8e radv/nir_lower_fs_intrinsics: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig 184557932f radv/nir_lower_intrinsics_early: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig a589bae3aa radv/nir_lower_fs_barycentric: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig 88587a3839 radv/nir_lower_view_index: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig c025a211f2 radv/nir_lower_viewport_to_zero: intrinsic pass 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33655>
 2025-02-24 20:19:10 +00:00
Alyssa Rosenzweig 2504e7951b treewide: use nir_shader_tex_pass 
Adapted the Coccinelle rules from the nir_shader_intrinsics_pass commit a while
ago, which was buggy then and buggy now, so then I fixed stuff up manually
(including formatting).

Via Coccinelle patch:

    @def@
    typedef bool;
    typedef nir_builder;
    typedef nir_instr;
    typedef nir_def;
    identifier fn, instr, intr, x, builder, data;
    @@

    static fn(nir_builder* builder,
    -nir_instr *instr,
    +nir_tex_instr *intr,
    ...)
    {
    (
    -   if (instr->type != nir_instr_type_tex)
    -      return false;
    -   nir_tex_instr *intr = nir_instr_as_tex(instr);
    |
    -   nir_tex_instr *intr = nir_instr_as_tex(instr);
    -   if (instr->type != nir_instr_type_tex)
    -      return false;
    )

    <...
    (
    -instr->x
    +intr->instr.x
    |
    -instr
    +&intr->instr
    )
    ...>

    }

    @pass depends on def@
    identifier def.fn;
    expression shader, progress;
    @@

    (
    -nir_shader_instructions_pass(shader, fn,
    +nir_shader_tex_pass(shader, fn,
    ...)
    |
    -NIR_PASS_V(shader, nir_shader_instructions_pass, fn,
    +NIR_PASS_V(shader, nir_shader_tex_pass, fn,
    ...)
    |
    -NIR_PASS(progress, shader, nir_shader_instructions_pass, fn,
    +NIR_PASS(progress, shader, nir_shader_tex_pass, fn,
    ...)
    )

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> [v3d]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Georg Lehmann 940e87f225 nir/opt_remove_phis: use nir_shader_phi_pass 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Georg Lehmann e4f0de89a5 nir/opt_phi_precision: use nir_shader_phi_pass 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Georg Lehmann 5a0702f351 nir/builder: add nir_shader_phi_pass 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
Alyssa Rosenzweig dda2dadb98 nir/builder: add nir_shader_tex_pass 
after the intrinsic and ALU passes. why not?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33672>
 2025-02-24 19:33:26 +00:00
David Rosca 367735551d frontends/vdpau: Use extra reference buffer for AV1 film grain 
AV1 applies film grain to decode target only, references in DPB must be
stored without film grain.
Fixes film grain decoding on drivers that use decode target buffers
directly for references.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33640>
 2025-02-24 19:04:53 +00:00
Georg Lehmann 5da76df4cd nir/search_helpers: check tex source type in is_only_used_as_float 
Foz-DB Navi21:
Totals from 164 (0.21% of 79377) affected shaders:
Instrs: 197477 -> 197035 (-0.22%); split: -0.23%, +0.01%
CodeSize: 1052944 -> 1051140 (-0.17%); split: -0.18%, +0.01%
VGPRs: 8104 -> 8080 (-0.30%)
Latency: 1115663 -> 1115567 (-0.01%); split: -0.06%, +0.05%
InvThroughput: 265822 -> 265158 (-0.25%); split: -0.26%, +0.01%
VClause: 3792 -> 3789 (-0.08%); split: -0.11%, +0.03%
SClause: 5738 -> 5744 (+0.10%); split: -0.02%, +0.12%
Copies: 12223 -> 12200 (-0.19%); split: -0.53%, +0.34%
PreVGPRs: 6807 -> 6801 (-0.09%); split: -0.15%, +0.06%
VALU: 139206 -> 138785 (-0.30%); split: -0.31%, +0.01%
SALU: 27852 -> 27853 (+0.00%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33674>
 2025-02-24 16:34:53 +00:00
Georg Lehmann 3d8585e4fc nir/search_helpers: look through vecs in is_only_used_as_float 
Will be useful with the next commit, or for backends that don't lower
alu to scalar.

No changes on Navi21.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33674>
 2025-02-24 16:34:53 +00:00
Georg Lehmann e0cebac14f nir/opt_algebraic: optimize b2f(a != 0) * a 
Just D3D9 things.

Foz-DB Navi21:
Totals from 137 (0.17% of 79377) affected shaders:
MaxWaves: 3366 -> 3370 (+0.12%); split: +0.24%, -0.12%
Instrs: 76462 -> 72091 (-5.72%)
CodeSize: 411584 -> 380792 (-7.48%)
Latency: 279472 -> 275505 (-1.42%); split: -2.01%, +0.59%
InvThroughput: 71311 -> 65369 (-8.33%)
VClause: 1587 -> 1612 (+1.58%); split: -1.01%, +2.58%
SClause: 1111 -> 1105 (-0.54%); split: -1.08%, +0.54%
Copies: 5621 -> 5602 (-0.34%); split: -1.39%, +1.05%
PreSGPRs: 5266 -> 5241 (-0.47%); split: -0.51%, +0.04%
PreVGPRs: 4249 -> 4236 (-0.31%); split: -0.35%, +0.05%
VALU: 50049 -> 45901 (-8.29%)
SALU: 8948 -> 8818 (-1.45%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33674>
 2025-02-24 16:34:53 +00:00
Mike Blumenkrantz e63acdd2b7 zink: force cached mem for streaming uploads 
it was previously possible to hit a path where an idle buffer with
non-cached mem could be directly mapped for streaming data uploads,
which kills perf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33678>
 2025-02-24 15:55:21 +00:00
Job Noorman 7210054db8 ir3: reformat after previous commit 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33701>
 2025-02-24 15:27:12 +00:00
Job Noorman 2fedc82c0c ir3: don't use deprecated NIR_PASS_V anymore 
Also replace OPT_V with OPT while we're at it.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33701>
 2025-02-24 15:27:12 +00:00
Job Noorman 0f69ada3b5 ir3/lower_tess: make all NIR passes report progress 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33701>
 2025-02-24 15:27:11 +00:00
Thomas H.P. Andersen 7276191d59 nvk: use a valid allocation scope 
VK_OBJECT_TYPE_DESCRIPTOR_POOL is used in vk_zalloc2 as allocation scope.
This should probably have been object scope.

Fixes: 607686f6bf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33697>
 2025-02-24 14:44:33 +00:00
Rhys Perry 2a3dce1b59 ac/nir: fix tess factor optimization when workgroup barriers are reduced 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: b49eab68a8 ("ac/nir: use s_sendmsg(HS_TESSFACTOR) to optimize writing tess factors for gfx11")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12632
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33645>
 2025-02-24 14:07:40 +00:00
Valentine Burley 5a510aede7 anv/ci: Increase parallelism of zink-anv-adl 
With some of the jobs migrated to the new brask and nissa devices, we can
increase zink-on-anv coverage on brya. Reduce the fraction of Piglit
tests and introduce fractional GLESCTS testing.

Also increase the parallelism of the zink nightly job, but lower its
FDO_CI_CONCURRENT variable to avoid OOMkills. To accommodate this,
decrease the parallelism of the anv-adl-full job.

Additionally, drop redundant HWCI_START_WESTON from full runs that
inherit the variable from their pre-merge jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley 318bc2ef03 intel/ci: Migrate intel-adl-cl and intel-adl-skqp to nissa 
Move the piglit CL and SKQP jobs to the new nissa devices. Nissa is
significantly slower than brya, so increase parallelism and timeout
accordingly.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley cb9875ce1b anv/ci: Migrate anv-adl-angle job to brask 
Move the ANGLE job to the new brask devices. Brask is significantly
slower than brya, so increase the parallelism accordingly.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley 2a3c373824 intel/ci: Add brask and nissa 
Add two new device types in LAVA, brask and nissa. These ADL devices will
be used to offload some of the jobs from brya.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley 85f9088d13 intel/ci: Honor device-specific FDO_CI_CONCURRENT variables 
FDO_CI_CONCURRENT was getting overwritten by .intel-common-test
inheriting FDO_CI_CONCURRENT: 6 from .lava-test, so change the order of
these definitions to fix that.

This change unfortunantely means that GPU_VERSION has to be overwritten
in some cases.

Additionally, drop redundant .anv-test where .anv-angle-test is used.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00
Valentine Burley 38fc58107a anv/ci: Update expectations from latest nightly 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33671>
 2025-02-24 13:36:10 +00:00