Commit Graph

59098 Commits

Author SHA1 Message Date
Martin Roukala (né Peres)
77c3df53ae zink/ci: update the radv expectations
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:04 +00:00
Martin Roukala (né Peres)
c69e2849a6 zink/ci: increase the parallelism of zink-radv-vangogh-valve
It current takes 17 minutes to run this job, which is above the 15
minutes target for Mesa CI. Let's increase the parallelism to reduce
exec time to closer to 13 minutes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:04 +00:00
Gert Wollny
3ddbf64e41 virgl: Lower binding start into buffer indices
This requires that we limit the number of max combinded SSBOs to 31,
otherwisewe shaders that use SSBO binding points with higher values
will break on the host.

Fixes CTS:
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case1
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case2
  KHR-GL43.shader_storage_buffer_object.advanced-indirectAddressing-case2
  KHR-GL43.shader_storage_buffer_object.advanced-usage-case1
  KHR-GL43.shader_storage_buffer_object.advanced-usage-sync
  KHR-GL43.shader_storage_buffer_object.advanced-matrix

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
99416624e5 ntt: add option to lower SSBO bindings to buffer index
When a shader uses SSBOs in various shader stages, then we have to track
the binding locations in order to be able to properly bind these SSBOs.

Therefore add a flag that enables adding the start index of the bindings to
the SSBO index.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
1247b23f28 virgl: Don't try to do re-alloc or readback by transfer for blob resources
Blob resources are mapped directly, no need to copy data around, and
in any case, neither the resource nor the transfer info will have an
IOV attached to it, so the transfer would result error out on the host
anyway.

In addition, blob resources should not use re-allocation.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
831e7818aa virgl: Enable AMD_vertex_shader_(layer|viewport_index) when host supports it
This increase the number of cases when the texture upload from buffer
can use the PBO upload code path.

v2: Fix logic combination (Corentin)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Qiang Yu
51e725df29 radeonsi: monolithic TCS emit tessfactor in nir directly
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:31 +00:00
Qiang Yu
3f5d42a28a radeonsi: lower nir_load_ring_tess_factors_offset_amd
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
719366c2b2 ac/llvm,radeonsi: lower nir_load_ring_tess_factors_amd
No one implement this intrinsic in llvm, so remove the
llvm entry too.

This will be used in TCS nir tess factor write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Alyssa Rosenzweig
f2617944bf panfrost: Don't round up Midgard polygon list BOs
Rounding up the polygon list BO can waste large amounts of memory. In a common
case I observed, it rounded up 11MB to 16MB, wasting 5MB. That adds up quickly
across processes, especially on the 2GB machines.

This only applies to Midgard. On Bifrost and newer, the driver does not
explicitly allocate this data structure. Cc stable because this rounding is
incorrect and the increase in RAM usage can cause real problems (especially
given how slow the shrinker is).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21831>
2023-03-16 04:13:46 +00:00
Rob Clark
a66c62420e driconf: Add ignore_discard_framebuffer option
Some apps use glDiscardFramebuffer()/glInvalidateFramebuffer() when they
only kidding.  Add a knob to disable that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21916>
2023-03-16 00:56:37 +00:00
Mark Janes
a2e5e7daa0 intel: use generated helpers for Wa_1409433168/Wa_16011107343
HSD 1306463417 is a hardware defect.  The originating software
workaround for the issue is Wa_1409433168.  Convert all references to
the software workaround number, and use generated helpers instead of
GFX comparisons.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21914>
2023-03-15 23:31:08 +00:00
Mike Blumenkrantz
f99eab23ad aux/trace: delete GALLIUM_TRACE_NIR log message
this is not only annoying, it breaks trace xml output

cc: mesa-stable

Acked-by: Simon Zeni <simon@bl4ckb0ne.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21609>
2023-03-15 20:43:52 +00:00
antonino
1538a28803 zink: fix final_hash update in zink_gfx_program_update
The logic that updates `ctx->gfx_pipeline_state.final_hash` assumed that
the program is replaced. It is supposed to xor `final_hash` with the
hash first and then with the new hash however when the program is
updated it end up xor-ing the new hash twice so it does nothing.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Fixes: 15450d2c2e ("zink: incrementally hash all pipeline component hashes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21925>
2023-03-15 18:00:20 +00:00
SoroushIMG
78198d634d zink: Add driver name and API version to renderer name
Having driver name in the renderer will be useful to differentiate
between open source and proprietary drivers as they can have different
feature sets/quirks.

Vulkan API version is also added to the name to match up with ANGLE.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21922>
2023-03-15 17:40:16 +00:00
Mike Blumenkrantz
81a4163375 zink: fix copy box merging adjacency
these cases need to increase the box size, not just adjust the offset

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21921>
2023-03-15 16:42:19 +00:00
Mike Blumenkrantz
32f74c4db5 zink: fix copy box iteration when adding
need to use the iterator, not the base pointer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21921>
2023-03-15 16:42:19 +00:00
Marek Olšák
999b956ebc radeonsi: correct an assertion if we get a display list with no vertex buffers
It's possible to get a display list with no vertex buffers if the linker
eliminates all VS inputs or if the list was built with glArrayElement with
no enabled attribs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
9fad7ca659 radeonsi: don't use fp16_rtz for FP formats in the compute blit
It doesn't change the test results.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
bcdde99675 radeonsi: don't convert to fp16 in the compute blit if not testing
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
e7d7fc6740 radeonsi: fix AMD_TEST=computeblit being rejected on gfx < 11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
f67b41e53b radeonsi: don't print the base non-view texture format for AMD_TEST=computeblit
it's confusing in the output and it affects nothing

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
f8070b3dc2 radeonsi: add AMD_DEBUG=nowcstream to enable caching for stream_uploader
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
e32700c503 radeonsi: rework MSAA resolve averaging to exploit instruction-level parallelism
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
1d978917a0 radeonsi: remove duplicated gfx11 check in si_msaa_resolve_blit_via_CB
The function really does that twice. You'll find the same code a few lines
above this change.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
d76bb15c51 radeonsi: replace nonir,noir,noasm,preoptir options with new reworked options
New options depending on what you want to print:
- initnir  = initial NIR of shader CSOs
- nir      = final NIR of variants after all lowering
- initllvm = LLVM IR before optimizations
- llvm     = final LLVM IR
- asm      = asm

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
c3df9973a3 radeonsi: dump shader stats only if dumping asm shaders
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Marek Olšák
c2f3339783 radeonsi: remove unused TCS/TES SGPR fields
We stopped using them when we switched to ac_nir_lower_hs_outputs_to_mem.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
2023-03-15 13:16:34 +00:00
Alyssa Rosenzweig
e6f9444567 asahi: Fix occlusion query lifetime
Theoretical lifetime issue, now easy to hit with the batch sync changes. Fixes
memory badness.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21857>
2023-03-15 08:46:09 +00:00
Emma Anholt
343426b95c ci/zink: Update TGL xfails/flakes based on the last nightly pipelines.
The 2f8073f87c fix changed some results, qbo
changed a week or so ago, and spec@ext_texture_array@compressed
texsubimage pbo has been crashing for a long time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21879>
2023-03-15 08:15:36 +00:00
Patrick Lerda
aba16defa8 radeonsi: fix memory leak related to ureg_get_tokens()
Indeed, ureg_get_tokens() returns an allocated string that should be
freed using ureg_free_tokens().

For instance, with "piglit/bin/arb_shader_image_load_store-invalid -auto -fbo"
Direct leak of 768 byte(s) in 2 object(s) allocated from:
    #0 0x7fa819a78b48 in __interceptor_realloc (/usr/lib64/libasan.so.6+0xb1b48)
    #1 0x7fa80e189e04 in tokens_expand ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:239
    #2 0x7fa80e189e04 in get_tokens ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:262
    #3 0x7fa80e191f6e in copy_instructions ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2079
    #4 0x7fa80e191f6e in ureg_finalize ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2129
    #5 0x7fa80e19447b in ureg_get_tokens ../src/gallium/auxiliary/tgsi/tgsi_ureg.c:2206
    #6 0x7fa80ec68b91 in si_create_fmask_expand_cs ../src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c:564

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21871>
2023-03-15 06:41:28 +00:00
Emma Anholt
761bbb2c6f ci: Update trace expectations for GLSL constant prop removal.
Somewhere along the way there were minor pixel value changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21751>
2023-03-15 03:29:19 +00:00
Emma Anholt
e395e57f07 glsl: Delete constant-variables pass.
Now that we don't do GLSL IR constant propagation or constant folding, we
can leave constant variable detection and handling to NIR.  This also
avoids some OOB array access in GLSL IR in a piglit test!

Freedreno stats again look like noise:

total instructions in shared programs: 2718412 -> 2718746 (0.01%)
instructions in affected programs: 80497 -> 80831 (0.41%)
total last-baryf in shared programs: 110015 -> 110510 (0.45%)
last-baryf in affected programs: 35263 -> 35758 (1.40%)
total full in shared programs: 189486 -> 189480 (<.01%)
full in affected programs: 52 -> 46 (-11.54%)
total constlen in shared programs: 494540 -> 494496 (<.01%)
constlen in affected programs: 452 -> 408 (-9.73%)
total sstall in shared programs: 198297 -> 197928 (-0.19%)
sstall in affected programs: 3691 -> 3322 (-10.00%)
total systall in shared programs: 432150 -> 431799 (-0.08%)
systall in affected programs: 6070 -> 5719 (-5.78%)
total waves in shared programs: 435098 -> 435110 (<.01%)
waves in affected programs: 92 -> 104 (13.04%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21751>
2023-03-15 03:29:19 +00:00
José Roberto de Souza
a10388224d iris: Move iris_bufmgr_init_global_vm() to i915/iris_bufmgr.c and prepare for Xe KMD
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21887>
2023-03-15 02:05:58 +00:00
José Roberto de Souza
631756db56 iris: Drop usage of i915 EXEC_OBJECT_WRITE
The whole usage of this flag is to call iris_use_pinned_bo() with
writable argument, for that we don't need any i915_drm.h specific type.
IRIS_BLORP_RELOC_FLAGS_EXEC_OBJECT_WRITE could have any other value but
keeping the same as i915_drm.h.

With this we can drop 2 i915_drm.h imports from generic Iris code.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21887>
2023-03-15 02:05:58 +00:00
José Roberto de Souza
660877cf38 iris: Drop I915_EXEC_FENCE types
Those are i915_drm.h specific types and should not be in code paths
shared by i915 and Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21887>
2023-03-15 02:05:58 +00:00
Alyssa Rosenzweig
2bab56737c panfrost: Note glDrawRangeElements underflow
Hopefully this helps someone wiring up robustness later on.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21891>
2023-03-14 23:10:01 +00:00
Alyssa Rosenzweig
a0e9f9278d panfrost: Handle null textures robustly
This is really dumb.

But this fixes arb_shader_language_420pack-active-sampler-conflict on v7 which
otherwise dereferences a null pointer trying to access the nonexistant texture
arrays, or DATA_INVALID_FAULTs if you give it a texture array filled with
zeroes. But it seems happy if you bind in null textures. This is dumb but less
faults in Piglit is good for reducing flakes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21891>
2023-03-14 23:10:01 +00:00
Alyssa Rosenzweig
7dda731a38 panfrost: Assert that we don't see unsupported vertex formats
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21891>
2023-03-14 23:10:00 +00:00
Alyssa Rosenzweig
62497d4860 util/prim_convert: Don't set index_bounds_valid
draw->index_bounds_valid tells drivers that the values of min_index/max_index
are set correctly and can be used e.g. to allocate memory for varyings. If set
incorrectly, the GL promises badness.

But, with primconvert, we go mucking with index buffers and then never update
the bounds. So it doesn't matter if the original index bounds were valid, we
can't promise the original bounds are *still* valid. If we were trying to
optimize CPU overhead, we could try to preserve the new min/max index but seeing
as only older Mali cares about this flag, and if you're using primconvert you're
already screwed, I'm not too inclined to go rework primconvert.

Fixes* page faults in primitive-restart-draw-mode on Mali-G52 for GL_QUAD_STRIPS
and GL_POLYGON, which hit the primconvert path. The full dmesg splat looks like:

[ 5438.811727] panfrost ffe40000.gpu: Unhandled Page fault in AS0 at VA 0x000000100A16BAC0
             Reason: TODO
             raw fault status: 0x25002C1
             decoded fault status: SLAVE FAULT
             exception type 0xC1: TRANSLATION_FAULT_1
             access type 0x2: READ
             source id 0x250

Notice that a high bit is randomly set in the address, this is trying to read
a varying from the actual varying buffer in the vicinity of 0xa16bac0. What's
actually happening is that we're trying to read index #0 despite promising the
driver a minimum index of 2, causing an integer underflow as we try to read
index -2, or as the hardware sees, 4294967294.

As long as we stop lying to panfrost about the bounds being correct, panfrost is
able to calculate the real (post-primconverted) bounds on its own, fixing the
test.

* Alternatively, maybe Panfrost should just ignore this bit, in which I don't
  know why we have it in Gallium, since it's probably not conformant to fault on
  out-of-range glDrawRangeElements.

Fixes: 72ff53098c ("gallium: add pipe_draw_info::index_bounds_valid")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21891>
2023-03-14 23:10:00 +00:00
Mike Blumenkrantz
2409ddb5db zink: fix copy box iteration
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21907>
2023-03-14 21:25:55 +00:00
Martin Roukala (né Peres)
10e0c5fd46 ci/b2c: move away from the hand-rolled initscript
Up until now, we have been handrolling part of the init-stage2.sh in
the b2c command line. Let's stop doing that and instead use the same
script as every other HW farms.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21872>
2023-03-14 17:22:07 +00:00
SoroushIMG
4affc3b361 zink: rename shadow key to zs swizzle
No functional change.

The shadow shader swizzle pass has been extended to optionally
include all z/s textures.
Rename the structs/variables to reflect this now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:30 +00:00
SoroushIMG
24a2530ed8 zink: workaround undefined swizzle 1 for z/s textures
using swizzle 1 with z/s textures returns undefined data
on some Imagination hardware.
Work around this by using the same shader swizzling used for
shadow samplers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:30 +00:00
SoroushIMG
2cf117ee39 zink: add depth/stencil needs shader swizzle workaround field
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:30 +00:00
SoroushIMG
cc15dbc4f8 zink: extend shadow swizzle pass to all zs textures
if needs_zs_shader_swizzle is used, apply constant swizzles to all
depth/stencil textures and not just shadow samplers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:30 +00:00
SoroushIMG
79557c2747 zink: add needs_zs_shader_swizzle shader key
This will be used later, but for now it should always be disabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:30 +00:00
SoroushIMG
b707cdccf5 zink: minor formatting change
that line was becoming too long.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:30 +00:00
SoroushIMG
f7257b1c75 zink: track shadow swizzle for all shader stages
this will be used later on to enable the pass in all
shader stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:29 +00:00
SoroushIMG
a83e63437f zink: fix shadow mask change logic when binding sampler views
First make sure shadow mask change sets dirty state.
Second move shadow mask bit removal to unbind_samplerview which
is cleaner and correctly clears the shadow bit when binding buffer texture.

Fixes: 5193f4f712 ("zink: add a fs shader key member to indicate depth texturing mode")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>
2023-03-14 17:03:29 +00:00