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6428 Commits

Author SHA1 Message Date
Rob Clark 72db4e51f3 isaspec: Fix comment 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
 2021-09-29 22:59:43 +00:00
Rob Clark cd3ee83ca5 isaspec: Remove unused leftovers 
These were never used, leftovers from an earlier iteration of isaspec
which used an RPN based thing for expressions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
 2021-09-29 22:59:43 +00:00
Lionel Landwerlin 52c0e6e5b3 spirv: switch Groups capability to non AMD specific field 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13081>
 2021-09-29 15:40:20 +00:00
Lionel Landwerlin daa8a81d99 nir: fix opt_memcpy src/dst mixup 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f6667cb0ce ("nir: Add a memcpy optimization pass")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13079>
 2021-09-28 16:36:08 +00:00
Lionel Landwerlin f349c8ab4b spirv: don't bother initializing variables to Undef 
If an OpVariable's initializer is undef, there is no need to
initialize the variable.

v2: Comment the code (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13030>
 2021-09-27 19:04:42 +00:00
Lionel Landwerlin a17d24d901 spirv: workaround LLVM-SPIRV Undef variable initializers 
The LLVM-SPIRV translator creates variables with initializers, but
most of those are actually undef initializers. We can just skip
composites that are entirely made of undefs, but for partially undefs,
we will still zero initialize.

v2: Rename wa_llvm_spirv_undef_initializer to wa_llvm_spirv_ignore_workgroup_initializer (Caio)
    Limit workaround to OpenCL (Caio)
    Make workaround clearer (Caio)

v3: Only apply workaround on workgroup storage (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13030>
 2021-09-27 19:04:42 +00:00
Lionel Landwerlin a17928639d spirv: avoid shadowing local variable 
v2: rename s/eval/elem_val/ (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13030>
 2021-09-27 19:04:42 +00:00
Lionel Landwerlin 9d9e67d118 spirv: don't fail on CapabilitySubgroupDispatch if supported 
Since only Anv uses the value, I'm only enabling this on anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 518693c3ec ("spirv: Handle the SubgroupSize execution mode")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13034>
 2021-09-24 20:23:14 +00:00
Rhys Perry e43007af56 nir/opt_if: add opt_if_rewrite_uniform_uses 
Turns:
if (a == (b=readfirstlane(a)))
   use(a)
into:
if (a == (b=readfirstlane(a)))
   use(b)

Improves divergence analysis and lets us scalarize use(a). Improves
Cyberpunk 2077 performance.

fossil-db (Sienna Cichlid, Cyberpunk 2077):
Totals from 57 (10.56% of 540) affected shaders:
VGPRs: 4904 -> 4040 (-17.62%)
CodeSize: 624360 -> 626828 (+0.40%); split: -0.06%, +0.46%
MaxWaves: 656 -> 824 (+25.61%)
Instrs: 119770 -> 119447 (-0.27%); split: -0.49%, +0.22%
Latency: 1950256 -> 1633110 (-16.26%); split: -16.26%, +0.00%
InvThroughput: 364852 -> 292089 (-19.94%)
VClause: 1512 -> 1008 (-33.33%)
SClause: 2693 -> 3196 (+18.68%)
Copies: 10050 -> 9955 (-0.95%); split: -3.34%, +2.40%
Branches: 3476 -> 3547 (+2.04%)
PreSGPRs: 4003 -> 5076 (+26.80%)
PreVGPRs: 4709 -> 3810 (-19.09%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12472>
 2021-09-24 18:41:18 +00:00
Rhys Perry 69f9a96af1 nir: add nir_src_components_read() 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12472>
 2021-09-24 18:41:18 +00:00
Caio Marcelo de Oliveira Filho 240e60ba76 nir/lower_io_to_vector: Allow Task/Mesh to load from outputs 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12951>
 2021-09-24 14:35:15 +00:00
Caio Marcelo de Oliveira Filho 895cfca641 spirv: Identify non-temporal memory access 
Map it to the existing ACCESS_STREAM_CACHE_POLICY access mode.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12945>
 2021-09-21 21:55:54 +00:00
Christian Gmeiner ca0f892191 compiler/isaspec: add alignment support 
This helps to get a really nice and aligend disasm output.
Just use :align=X to define where in the line the field
should be printed.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Christian Gmeiner eae96d0c4c compiler/isaspec: keep track of written data 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Christian Gmeiner f0104a6c72 compiler/isaspec: add print(..) helper 
To support field alignment we need to keep track of how much
data we have printed to our out FILE. This is a prep commit.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Christian Gmeiner bc2e806b0f freedreno/isa: move isaspec to a new home 
This commit moves isaspec out of freedreno into a more
generic new home - src/compiler/isaspec.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Christian Gmeiner 3d65cea6ee util/bitset: s/BITSET_SET_RANGE/BITSET_SET_RANGE_INSIDE_WORD 
Prep work for the next commit.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Jason Ekstrand 518693c3ec spirv: Handle the SubgroupSize execution mode 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12959>
 2021-09-21 18:34:59 +00:00
Bas Nieuwenhuizen 0d8bd8518d nir: Support ray launch size in divergence analysis. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
 2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen 56b06c09b4 nir: Add AMD rt intrinsics. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
 2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen b6be96a2bd radv: Modify load_sbt_amd intrinsic to get the descriptor. 
That way we can get the address to the entry, which is needed for
some nir builtins because extra data in the entry can be used as
shader input.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
 2021-09-21 01:53:39 +00:00
Timur Kristóf 872d21820f nir: Exclude non-generic patch variables from get_variable_io_mask. 
These are I/O variables which are not going to be removed anyway.
However, get_variable_io_mask handles their location incorrectly.

Found using the GCC undefined behavior sanitizer.
Fixes the following error:

runtime error:
shift exponent 4294967258 is too large
for 64-bit type 'long unsigned int'

Closes: #5319
Fixes: cf5f8f55c3
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
 2021-09-20 18:08:16 +00:00
Ian Romanick d7ba52cce9 nir/edgeflags: Add a flag to indicate the edge flag input is needed 
Most modern hardware needs the edge flag added as a hidden vertex input
and needs code added to the vertex shader to copy the input to an
output.  Intel hardware is a little different.  Gfx4 and Gfx5 hardware
works in the previously described mannter.  Gfx6+ hardware needs the
edge flag as a specific vertex shader input, and that input is magically
processed by fixed-function hardware without need for extra shader code.

This flag signals only that the vertex shader input is needed.  It would
be nice if we could decouple adding the vertex shader input from
generating the copy-to-output code, but that has proven to be
challenging.  Not having that code causes other passes to want to
eliminate that shader input.

v2: Convert conditional to assertion.  This pass is only called for
vertex shaders.  Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12858>
 2021-09-17 16:36:08 -07:00
Rhys Perry a1af902531 nir/algebraic: distribute fmul(fadd(a, b), c) when b and c are constants 
This allows for more MAD/FMA instructions to be created.

fossil-db (Sienna Cichlid):
Totals from 50134 (33.46% of 149839) affected shaders:
VGPRs: 2436536 -> 2436000 (-0.02%); split: -0.05%, +0.03%
SpillSGPRs: 13136 -> 13135 (-0.01%); split: -0.02%, +0.02%
CodeSize: 206621424 -> 206278292 (-0.17%); split: -0.23%, +0.07%
MaxWaves: 1116804 -> 1117448 (+0.06%); split: +0.07%, -0.01%
Instrs: 38977460 -> 38862886 (-0.29%); split: -0.33%, +0.04%
Latency: 832425389 -> 827432260 (-0.60%); split: -0.63%, +0.03%
InvThroughput: 184193457 -> 183563350 (-0.34%); split: -0.37%, +0.03%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7458>
 2021-09-17 17:28:26 +00:00
Jason Ekstrand 6c7d23e6ca nir: Stop sweeping indirects 
They're no longer ralloc'd.

Fixes: 879a569884 "nir: Switch from ralloc to malloc for NIR instructions."
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12884>
 2021-09-16 11:28:36 +00:00
Jason Ekstrand d1eae6f36b nir: Properly clean up nir_src/dest indirects 
Now that they're no longer ralloc'd, we have to be much more careful
about indirects.  We have to make sure every time a source or
destination is overwritten, its indirect (if any) is freed.  We also
have to choose a memory ownership convention for the rewrite functions.
Assuming that they will be called with the source from some other
instruction, we choose to always make a copy of the indirect (if any).
It's the responsibility of the caller to ensure its copy of the indirect
is freed.

Unfortunately, all this extra logic is going to make
nir_instr_rewrite/move_src/dest more expensive because they now have
all the logic of nir_src/dest_copy instead of a simple struct
assignment.  Fortunately, the vast majority of rewrite calls are done by
nir_ssa_def_rewrite_uses which is an SSA-only fast-path.

Fixes: 879a569884 "nir: Switch from ralloc to malloc for NIR instructions."
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12884>
 2021-09-16 11:28:36 +00:00
Emma Anholt aed4c0b5a9 nir: Drop the unused instr arg for src/dest copy functions. 
Now that we don't use ralloc, we don't need this arg to get at the right
ralloc ctx.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:06 +00:00
Emma Anholt 879a569884 nir: Switch from ralloc to malloc for NIR instructions. 
By replacing the 48-byte ralloc header with our exec_node gc_node (16
bytes), runtime of shader-db on my system across this series drops
-4.21738% +/- 1.47757% (n=5).

Inspired by discussion on #5034.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:06 +00:00
Emma Anholt feee5e6974 nir/tests: Fix transmuting an SSA dest to be non-SSA 
With the de-ralloc changes, having the register dest not have its .reg
properly initialized caused crashes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:06 +00:00
Emma Anholt 1edff520e2 nir/lower_phis_to_scalar: Use nir_instr_free() to free instrs. 
Preparation for de-rallocing instrs.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:06 +00:00
Emma Anholt d1a2870f78 nir: Add all allocated instructions to a GC list. 
Right now we're using ralloc to GC our NIR instructions, but ralloc has
significant overhead for its recursive nature so it would be nice to use a
simpler mechanism for GCing instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:06 +00:00
Emma Anholt 22788d68eb nir: Consistently pass the instr to nir_src_copy(). 
The arg says it's supposed to be the instr, not the shader.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:05 +00:00
Emma Anholt 5e37cfb7fe nir: Consistently pass the shader to the shader arg of instr creation. 
We were using the ralloc parent in some places, which should work out to
be the shader I think, but to de-ralloc the instrs we should just pass the
existing shader pointer in.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:05 +00:00
Emma Anholt 7a4bbe60c1 nir/from_ssa: Use nir_instr_free() to free instrs instead of ralloc. 
This code was being tricky with passing a mem_ctx instead of the shader,
then freeing the mem_ctx when the pass was done and all the parallel
copies had been removed from the shader.  Use the right type for instr
creation and do a bit of manual list management to prepare the way for
non-ralloc NIR instrs.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:05 +00:00
Emma Anholt b99efb8af0 nir: Pull the instr list free function out to a helper. 
With the de-rallocing, we're going to have some more places that free a
list of instrs.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:05 +00:00
Emma Anholt 36d9bdca0b nir: Add a nir_instr_free() to replace ralloc_free(instr). 
This will gain another step shortly.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11776>
 2021-09-14 17:53:05 +00:00
Ian Romanick 7956a701d8 nir/lower_gs_intrinsics: Make nir_lower_gs_intrinsics be idempotent 
Calling this lower pass twice in a row would cause spurious
set_vertex_and_primitive_count(0, undef) intrinsics after the proper
set_vertex_and_primitive_count intrinsic.  This pretty much turns any
geometry shader into garbage.

Fix this by treating nir_intrinsic_emit_vertex_with_counter and
nir_intrinsic_end_primitive_with_counter just like the non-_with_counter
versions.  If no blocks would need set_vertex_and_primitive_count
intrinsics added, exit the pass before doing any work.  This prevents
the need for DCE to do extra clean up later.

Since this pass is potentially called multiple times via multiple
invocations of a finalize_nir callback, it is (hypothetically?) possible
that control flow could be changed to add new blocks that need this
intrinsic.  The check implemented in this commit should be robust
against that possibility.

v2: Add a_block_needs_set_vertex_and_primitive_count.  Suggested by
Timur.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12802>
 2021-09-14 09:13:07 -07:00
Ian Romanick edf357b233 nir/lower_gs_intrinsics: Return progress if append_set_vertex_and_primitive_count makes progress 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 542d40d698 ("nir: Add new GS intrinsics that maintain a count of emitted vertices.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12802>
 2021-09-14 09:12:47 -07:00
Mike Blumenkrantz 361a7d2451 compiler/spirv: add a fail if tex instr coord components aren't dimensional enough 
this is really hard to pin down later on, so catch it here instead

gotta have those dimensions.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12825>
 2021-09-14 13:54:24 +00:00
Kenneth Graunke d3b72d49cb glsl: Assert that lower_blend_equation_advanced is only called for FS 
It only makes sense to call this pass for fragment shaders, and the
first thing the pass does is read a FS-specific field out of a union,
so it isn't safe to call it for other shader stages.

We could make it early return, but instead we just assert, so that
drivers know to only call it when appropriate.

(A previous version of this patch, which early returned instead of
asserting, was Reviewed-by: Emma Anholt <emma@anholt.net> as well.)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12839>
 2021-09-14 03:55:05 +00:00
Emma Anholt 91dc863921 mesa: Move the advanced blend bitmask to shader_info. 
For drivers that don't lower advanced blend to FBFETCH, we need the
bitmask to be in the NIR shader so that it gets carried over to TGSI
successfully.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12813>
 2021-09-13 18:36:58 +00:00
Bas Nieuwenhuizen b05cd10b8e nir: Avoid visiting instructions multiple times in nir_instr_free_and_dce. 
Sadly need to poke a bit in the src internals to avoid using yet another
heap allocated datastructure.

Fixes: 5251548572 ("nir: Add a nir_instr_remove that recursively removes dead code.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5323
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12726>
 2021-09-09 21:35:03 +00:00
Rhys Perry c1f724b2b9 nir: fix serialization of loop/if control 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes: e76ae39ae2 ("nir: add support for user defined select control")
Fixes: b56451f82c ("nir: add support for user defined loop control")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12778>
 2021-09-09 10:32:30 +00:00
Qiang Yu 7054c1b7fd nir/linker: pack varyings with different interpolation qualifier 
Driver like radeonsi load varying in a scalar manner, so prefer to pack
varying with different interpolation qualifier into same slot to save
space.

But driver like panfrost/bifrost can load varying in vector manner,
so prefer to pack varying with same interpolation qualifier.

Driver can add interpolation qualifiers which are able to be
packed into same varying slot to pack_varying_options nir option.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12537>
 2021-09-09 06:00:58 +00:00
Qiang Yu 5a24aed1ac nir/lower_io_to_vector: check centroid & sample when merge variable 
These qualifiers should be respected for different varying load code
generation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12537>
 2021-09-09 06:00:58 +00:00
Marcin Ślusarz 30b2cc423c glsl: break out early if compound assignment's operand errored out 
Fixes compiler crashes on:

struct Foo
{
  float does_exist_member;
};

in vec2 tex;
out vec4 color;

void
main(void)
{
  Foo foo;

  foo.does_not_exist_member %= 3; /* or any of: <<=, >>=, &=, |=, ^= */
  color = vec4(tex.xy, tex.xy);
}

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
CC: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12717>
 2021-09-08 06:59:34 +00:00
Marcin Ślusarz 26302ccdc1 glsl: propagate errors from *=, /=, +=, -= operators 
Fixes compiler crash on:

void main()
{
    gl_FragColor = a += 1;
}

(a is not declared anywhere)

Found with AFL++.

Fixes: d1fa69ed61 ("glsl: do not attempt assignment if operand type not parsed correctly")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12717>
 2021-09-08 06:59:34 +00:00
Timothy Arceri 52893327fb glsl: fix variable scope for do-while loops 
Without this the following code was successfully compiling.

   void main()
   {
      do
         int var_1 = 0;
      while (false);

      var_1++;
   }

Fixes: a87ac255cf ("Initial commit.  lol")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12465>
 2021-09-08 03:56:59 +00:00
Timothy Arceri 174c057926 glsl: handle scope correctly when inlining loop expression 
We need to clone the previously evaluated loop expression when
inlining otherwise we will have conflicts with shadow variables
defined in deeper scopes.

Fixes: 5c02e2e2de ("glsl: Generate IR for switch statements")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5255

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12465>
 2021-09-08 03:56:59 +00:00
Timothy Arceri 8bbbbb02cd glsl: fix variable scope for loop-expression 
We need to evaluate the loop-expression of a for loop before
we evaluate the loop body otherwise we will find the wrong
variable for the following loop.

   int var_0 = 0;
   for(; var_0 < 10; var_0++) {
      const float var_0 = 1.0;
      gl_FragColor = vec4(0.0, var_0, 0.0, 0.0);
   }

Fixes: a87ac255cf ("Initial commit.  lol")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5262

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12465>
 2021-09-08 03:56:59 +00:00