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Author SHA1 Message Date
Samuel Pitoiset 72871d8330 radv: set missing FMASK surface counters for MSAA MRTs 
This has been removed few years ago by mistake but it's important for
performance. This is mostly for addrlib to determine tile_swizzle which
is used to make memory access faster with multiple render targets.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31797>
 2024-10-28 08:21:12 +01:00
Samuel Pitoiset aa19bf3d93 amd/descriptors: set fmask_tile_swizzle for TC-compat CMASK images on GFX8 
This is required.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31797>
 2024-10-28 08:21:12 +01:00
Vignesh Raman c3531d5fea ci: rename FORCE_KERNEL_TAG to EXTERNAL_KERNEL_TAG 
FORCE_KERNEL_TAG allows testing kernel uprevs without rebuilding
containers by supplying an external kernel directly for booting on
hardware devices. Renaming it to EXTERNAL_KERNEL_TAG clarifies its
purpose, distinguishing it from KERNEL_TAG which rebuilds containers.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31795>
 2024-10-28 02:18:27 +00:00
Jose Maria Casanova Crespo f47c692d99 v3dv/ci: Add missing fails on RPi4/5 for uprev VKCTS to 1.3.10.0 
Fixes: 38d7492391 ("ci: uprev VKCTS to 1.3.10.0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31866>
 2024-10-28 01:33:15 +00:00
Valentine Burley e18733300e anv/ci: Remove additive blending fails on ADL 
This was a VKCTS bug on earlier version of the CTS.

These tests have been actually passing since the VKCTS was uprevved to
1.3.9.0, which landed a bit before ADL testing in CI was turned on.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31862>
 2024-10-27 21:43:18 +00:00
Valentine Burley 3b5e49a7f8 intel/ci: Fix Alder Lake's configuration 
There's currently no GL or GLES testing on the iris gallium driver,
and the VKCTS expectations were erroneously listed under iris-*.txt.

Fix the rules set for anv-adl-full, change the GPU_VERSION to anv-adl
and move the expectations around accordingly.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31862>
 2024-10-27 21:43:18 +00:00
David Heidelberg 5b3f7de99f ci/freedreno: Introduce OpenCL testing for Adreno 618, 660, and 750 
Implement testing rusticl with piglit.

Piglit OpenCL support enablement already got merged.

Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:41 +00:00
Dmitry Baryshkov 4f1adb71d6 rusticl: Enable on freedreno 
To really use the driver, specify the environment variable:

  export RUSTICL_ENABLE=msm

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:41 +00:00
Rob Clark 63a5803433 freedreno/ir3: Do not propagate away a widening move 
A narrowing move from const is just emulated CONSTANT_DEMOTION_ENABLE so
we can permit it.  But not the inverse.

Cc: mesa-stable
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:41 +00:00
Rob Clark e89e89caeb freedreno/computerator: Make shader show up in devcore/etc 
Previously we were hitting the BO heap which isn't dumped because the
buffer was mappable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:41 +00:00
Rob Clark f58c1aebff ir3/ra: Better CL/kernel support 
With CL we do not know the local wg size at compile time.  Assuming the
worst-case (max) size limits the register footprint, leading to excess
spilling.  OTOH with CL the app queries the supported local size after
compiling the kernel.  So instead pick the largest warp size as the
target.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:41 +00:00
Rob Clark f3211e243f freedreno/a6xx: Support variable wg size 
If local wg size isn't known at compile time, we need to move some of
the state emit out of the state object and into IB2 cmdstream.

This still doesn't account for the fact that RA currently must assume
the worst case, meaning limiting cl kernels to a miniumum number of regs
and spilling excessively.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:41 +00:00
David Heidelberg 1569219f51 freedreno/ir3: Lower fisnormal op 
Avoid crash when running piglit test:
program@execute@builtin@builtin-float-isnormal-1.0.generated

Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:40 +00:00
Dmitry Baryshkov e20f02f64a freedreno/ir3: Lower the hadd operations 
There do not seem to be instructions for the ihadd/uhadd NIR operations.
Lower them to simpler ops.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:40 +00:00
Dmitry Baryshkov 8707c15b5b freedreno/ir3: Treat MESA_SHADER_KERNEL in the same way as compute 
In ir3_shader_descriptor_set() tread MESA_SHADER_KERNEL shaders in the
same way, as PIPE_SHADER_COMPUTE shaders, return 0.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30835>
 2024-10-27 14:04:40 +00:00
Iván Briano 13db5fad27 brw: fix task/mesh push constant loading 
The InlineData passed to the shader is a fixed size unrelated to the
register size. It happens to match pre-Xe2, but by considering it the
same in Xe2, we ended up reading pushed constants from the wrong place
when they didn't fit in the InlineData.

Fixes: 97b17aa0b1 ("brw/nir: rework inline_data_intel to work with compute")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31856>
 2024-10-26 18:12:41 +00:00
Jordan Justen b7560fa048 anv: Build for Xe3 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen 35ace9d4e2 intel/compiler: Xe2 and Xe3 use the same compaction tables 
Ref: bspec 56709
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen 688a673c5a intel/brw: Allow Xe3 in brw_stage_has_packed_dispatch() 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen efa7aa4e47 intel/dev: Add PTL PCI IDs (with FORCE_PROBE set) 
Ref: bspec 72574
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen bd52bef69e intel/dev: Add PTL device info 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen 6242b70354 intel/dev: Add INTEL_PLATFORM_PTL platform enum 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen cd33b7766a intel/compiler: Add compiler enum for Xe3 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen f59ae1ec10 intel/dev: Add Xe3 support to get_l3_list() 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen fa964dcadc iris: Build for Xe3 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen ae7619429e intel/shaders: Build for Xe3 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:30 +00:00
Jordan Justen 521d2299b8 intel/isl: Build for Xe3 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:29 +00:00
Jordan Justen acb1c45a8b intel/genxml: Start Xe3 support 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:29 +00:00
Jordan Justen 2d15c23e4a intel/dev: Add XE3_FEATURES macro 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:29 +00:00
Jordan Justen d476badb48 intel/dev: Support Xe3 device init (for intel_device_info_test) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838>
 2024-10-26 07:39:29 +00:00
Ian Romanick 04e1783278 brw: Call brw_fs_opt_algebraic less often 
No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31729>
 2024-10-25 23:39:36 +00:00
Ian Romanick ac64b78f1f brw/copy: Perform constant folding with constant propagation 
No shader-db or fossil-db changes on any Intel platform.

v2: Simlify the logic for when to try constant folding. Do
commute_immediates before constant folding. Both suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31729>
 2024-10-25 23:39:36 +00:00
Ian Romanick 2cc1575a31 brw/algebraic: Refactor constant folding out of brw_fs_opt_algebraic 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31729>
 2024-10-25 23:39:36 +00:00
Eric Engestrom 90ad5d3f06 ci: drop dead "load jwt in the environment just before exiting the job" code 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31855>
 2024-10-25 21:41:05 +00:00
Ian Romanick 5dcad54902 brw/sat: Convert nearly all tests to use new style builders 
v2: Use new style builder for second ADD in other_non_saturated_use
too.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
 2024-10-25 20:31:45 +00:00
Ian Romanick 19ae7aceb5 brw/sat: Fix small typos, copy and paste, etc. 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
 2024-10-25 20:31:45 +00:00
Ian Romanick de45273307 brw/builder: Add new style ALU3 builder 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
 2024-10-25 20:31:45 +00:00
Ian Romanick 8329c04521 brw/copy: Don't remove instructions w/ conditional modifier 
Fixes: 9e750f00c3 ("intel/brw: Make opt_copy_propagation_defs clean up its own trash")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
 2024-10-25 20:31:44 +00:00
Kenneth Graunke d949d47f09 brw/emit: Fix align16 3src subregister encodings for HF types 
Prior to Cherryview, align16 3src instruction sources had to have their
subregister number be DWord-aligned.  Cherryview added a discontiguous
bit in the encoding to represent bit 1 of the subregister number.  This
allows us to use packed HF sources.

Update the ISA encoding helpers to properly handle bit 1.  While we're
at it, make them take a full subregister number and adjust accordingly,
rather than making the callers divide or multiply by some alignment.

Note that the destination subregister must still be DWord aligned, so
HF destinations must be strided.

Thanks to Ian Romanick for discovering that we were botching this.

BSpec: 12054, 12081

v2 (idr): Fix ordering of high and low bit parameters to brw_inst_bits.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
 2024-10-25 20:31:44 +00:00
Kenneth Graunke 33cd5a49f1 brw/validate: Return an error for Align16 access mode on Icelake+ 
Gfx11+ doesn't support Align16 instructions anymore - only Align1 mode.

Bailing early for Align16 is important so that brw_hw_decode_inst
doesn't try to read Align16 related instruction fields on generations
where they no longer exist (which could trigger assertions).

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31834>
 2024-10-25 20:31:44 +00:00
Lionel Landwerlin 393ca64716 anv: avoid companion usage on RCS 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e98759c7f4 ("anv: Use RCS engine for copying stencil resource for gfx125")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31847>
 2024-10-25 19:06:18 +00:00
Dmitry Osipenko f83c2fcc98 ci/zink: Mark glx-multithread-clearbuffer flake on ADL 
The glx-multithread-clearbuffer test both fails and passes depending on
a Mesa build for ADL. This test is flaky in general for everyone in Mesa,
hence move to the flakes.

Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Dmitry Osipenko f76ed795de util/cache_test: Add mesa-db test for adding cache entry bigger than empty cache 
Add Mesa-DB regression test for a segfault bug that happened when a cache
entry bigger than size-limit of the cache is added to empty cache.

Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Dmitry Osipenko 5ec424c6be util/mesa-db: Fix crash on compacting empty DB 
Fix mesa_db_compact() segfaulting if compacted DB is empty. This crash
happens on writing cache entry that is bigger than DB's size limit and
when DB is empty, which can be triggered by setting DB size to a small
value.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Dmitry Osipenko 7b40d32187 util/mesa-db: Open DB files during access time 
Open DB files when DB is accessed and close them afterwards to reduce
number of FDs used by multi-part DB cache.

Fixes: fd9f7b748e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Dmitry Osipenko 2a9378a0f9 util/mesa-db-multipart: Open one cache part at a time 
Open one cache DB part at a time for a multi-part cache to reduce number
of FDs used by the cache. Previously multi-part DB cache instance was
consuming 100 FDs, now it's 2 and cache files are opened when cache
is read or written instead of opening them at the init time.

Fixes: fd9f7b748e ("util/mesa-db: Introduce multipart mesa-db cache")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11776
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Dmitry Osipenko 6a2f5cb556 util/mesa-db: Fix missing O_CLOEXEC 
Use O_CLOEXEC flag for opened cache DB files to not leak cache FDs when
process forks.

Fixes: 32211788d0 ("util/disk_cache: Add new mesa-db cache type")
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11810
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Michel Dänzer 92893309bc util/mesa-db: Further simplify mesa_db_compact 
Taking advantage of the persistent array of index entries. In
particular, it's no longer necessary to read from the index file during
compaction.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Michel Dänzer 031f2c2a69 util: Use persistent array of index entries 
Instead of allocating separate memory for each index entry in the hash
table, use a single array (backed by a mapping of anonymous memory
pages, which allows efficient array resizes) which holds a copy of the
index file contents.

The hash table now references each entry via its offset in the index
file, so that the array address can change on resize.

This eliminates some index file reads and reduces memory management
overhead for the hash table entries. It should be more efficient in
general.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00
Michel Dänzer feef4bf828 util/mesa-db: Use single read for whole index 
Instead of separate reads per index entry. Should be more efficient.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30988>
 2024-10-25 18:06:14 +00:00