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Author SHA1 Message Date
Timothy Arceri 726e8f24c6 glsl: move calculate_subroutine_compat() to shared linker code 
We will make use of this in the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-10 00:41:20 +00:00
Timothy Arceri c60d0bd92f glsl: call uniform resource checks from the nir linker 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-10 00:41:20 +00:00
Timothy Arceri 05c1f7a154 glsl: move uniform resource checks into the common linker code 
We will call this from the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-10 00:41:20 +00:00
Timothy Arceri b85985dd51 glsl: call check_subroutine_resources() from the nir linker 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-10 00:41:20 +00:00
Timothy Arceri a6fd1c7752 glsl: move check_subroutine_resources() into the shared util code 
We will make use of this in the nir linker in the following patch.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-10 00:41:20 +00:00
Jason Ekstrand 3dec68e682 genxml: Remove a non-existant HW bit 2020-01-09 18:40:20 -06:00
Kristian H. Kristensen f9d35ea55b ir3: Set up full/half register conflicts correctly 
Setting up transitive conflicts between a full register and its two
half registers (eg r0.x and hr0.x and hr0.y) will make the half
registers conflict.  They don't actually conflict and this prevents us
from using both at the same time.

Add and use a new ra helper that sets up transitive conflicts between
a register and its subregisters, except it carefully avoids the
subregister conflict.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
 2020-01-09 16:03:25 -08:00
Dave Airlie 85eed5def3 llvmpipe: add ARB_derivative_control support 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2020-01-10 08:43:40 +10:00
Marek Olšák 269953e779 radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9 
Fixes: 69ea473 "amd/addrlib: update to the latest version"
Closes: #2325

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-09 16:28:28 -05:00
Lionel Landwerlin 60e0db3bfb anv: fix intel perf queries availability writes 
The availability is not written at the location changed in
ee6fbb95a74d...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ee6fbb95a7 ("anv: Properly handle host query reset of performance queries")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
 2020-01-09 20:42:36 +02:00
Dylan Baker da2fe9c15e docs: Add release notes for 19.3.2, update calendar and home page 2020-01-09 10:33:49 -08:00
Dylan Baker 2d46a7f26d docs: add SHA256 sums for 19.3.2 2020-01-09 10:32:18 -08:00
Dylan Baker d4f237dcce docs: Add release notes for 19.3.2 2020-01-09 10:32:14 -08:00
Satyajit Sahu 4e3a09db25 radeon/vcn: Handle crop parameters for encoder 
Set proper cropping parameter if frame cropping is enabled

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Boyuan Zhang boyuan.zhang@amd.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
 2020-01-09 15:43:18 +00:00
Daniel Schürmann cd31da4587 nir: fix printing of var_decl with more than 4 components. 
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Fixes: a8ec4082a4 ('nir+vtn: vec8+vec16 support')
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320>
 2020-01-09 10:31:26 +01:00
Samuel Pitoiset e298e78a01 radv: advertise VK_AMD_shader_image_load_store_lod 
This extension allows to use LOD with image read/write operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2020-01-09 07:58:34 +01:00
Samuel Pitoiset 4d49a7ac73 aco: handle nir_intrinsic_image_deref_{load,store} with lod 
Use image_load_mip and image_store_mip respectively if the lod
parameter isn't zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2020-01-09 07:58:33 +01:00
Samuel Pitoiset e77ff89914 amd/llvm: handle nir_intrinsic_image_deref_{load,store} with lod 
Use image_load_mip and image_store_mip respectively if the lod
parameter isn't zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2020-01-09 07:58:33 +01:00
Samuel Pitoiset 1b808d208f spirv,nir: add new lod parameter to image_{load,store} intrinsics 
SPV_AMD_shader_image_load_store_lod allows to use a lod parameter
with OpImageRead, OpImageWrite and OpImageSparseRead.

According to the specification, this parameter should be a 32-bit
integer. It is initialized to 0 when no lod parameter is found
during SPIR-V->NIR translation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2020-01-09 07:58:33 +01:00
Samuel Pitoiset 37bfd854c7 spirv: add SpvCapabilityImageReadWriteLodAMD 
New SPIR-V capability for SPV_AMD_shader_image_load_store_lod.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2020-01-09 07:58:33 +01:00
Tapani Pälli 1e29ff7b3d mesa: create program resource hash in a single place 
This is a cleanup but also a fix for commit dd09f1d806. In case of
i965 we did not actually create hash for cached shader programs.

Fixes: dd09f1d806 "mesa/st/i965: add a ProgramResourceHash for quicker resource lookup"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2020-01-09 07:28:13 +02:00
Dave Airlie ee9879335e llvmpipe: add support for ARB_indirect_parameters. 
This just adds support for getting the draw count from the
indirect buffer.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
 2020-01-09 10:35:44 +10:00
Dave Airlie 315fa2e5c9 llvmpipe: enable driver side multi draw indirect 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
 2020-01-09 10:35:40 +10:00
Dave Airlie d10a3d528f gallium/util: add multi_draw_indirect to util_draw_indirect. 
ARB_indirect_parameters needs drivers to deal with mutli_draw_indirect
themselves.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
 2020-01-09 10:35:36 +10:00
Thong Thai 3a4f8c8158 mesa: Prevent _MaxLevel from being less than zero 
When decoding using VDPAU, the _MaxLevel value becomes -1 due to
NumLevels being equal to 0 at a certain point, and decoding fails
due to an assertion later on.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
 2020-01-08 16:44:20 -05:00
Marek Olšák 9b71041627 ac: add ac_build_s_endpgm 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 16:03:48 -05:00
Marek Olšák 1c44480538 ac: add 128-bit bitcount 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 16:00:41 -05:00
Marek Olšák d7b565365e ac/gpu_info: add pc_lines and use it in radeonsi 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 16:00:40 -05:00
Marek Olšák d1c8aeb24f ac: unify primitive export code 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 16:00:38 -05:00
Marek Olšák 1c77a18cc2 ac: unify build_sendmsg_gs_alloc_req 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 16:00:36 -05:00
Marek Olšák fd84e422b6 radeonsi: clean up messy si_emit_rasterizer_prim_state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:49 -05:00
Marek Olšák b64a3240c2 radeonsi: determine accurately if line stippling is enabled for performance 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:47 -05:00
Marek Olšák 79cc7e6ff0 radeonsi: test polygon mode enablement accurately 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:43 -05:00
Marek Olšák 898c9cb797 radeonsi: fix context roll tracking in si_emit_shader_vs 
probably harmless, because we don't need to track context rolls on gfx10

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:39 -05:00
Marek Olšák 4249a90f5d radeonsi: fix monolithic pixel shaders with two-sided colors and SampleMaskIn 
They are never used except for testing AMD_DEBUG=mono.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:35 -05:00
Marek Olšák 186335d17d ac/gpu_info: always use distributed tessellation on gfx10 
This might fix a hang on Navi14.

Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-08 15:48:32 -05:00
Marek Olšák eb1e10d0be gallium: bypass u_vbuf if it's not needed (no fallbacks and no user VBOs) 
This decreases CPU overhead, because u_vbuf is completely bypassed
in those cases.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2020-01-08 13:40:59 -05:00
Marek Olšák 9f6020abc6 gallium/cso_context: move non-vbuf vertex buffer and element code into helpers 
These will be reused.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2020-01-08 13:40:59 -05:00
Marek Olšák ce648b913f gallium: put u_vbuf_get_caps return values into u_vbuf_caps 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
 2020-01-08 13:40:59 -05:00
Jonathan Marek 472593e9cf etnaviv: remove unnecessary vertex_elements_state_create error checking 
PIPE_CAP_MAX_VERTEX_BUFFERS already sets the maximum vertex_buffer_index.

There's no need to error on num_elements == 0 (if that can even happen).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
 2020-01-08 12:27:35 -05:00
Jonathan Marek 76d93b437b etnaviv: implement gl_VertexID/gl_InstanceID 
Fixes:
dEQP-GLES3.functional.instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
 2020-01-08 12:27:35 -05:00
Jonathan Marek 93ff6f5919 etnaviv: HALTI2+ instanced draw 
Fixes:
dEQP-GLES3.functional.draw.draw_arrays_instanced.*
dEQP-GLES3.functional.draw.draw_elements_instanced.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
 2020-01-08 12:27:34 -05:00
Jonathan Marek ea608ae23b etnaviv: update headers from rnndb 
Update to etna_viv commit 46af5f1d.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
 2020-01-08 12:27:34 -05:00
Lionel Landwerlin 4578d4ae52 anv: don't close invalid syncfd semaphore 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
 2020-01-08 18:20:50 +02:00
Krzysztof Raszkowski 7d33203b44 gallium/swr: Fix glVertexPointer race condition. 
Sometimes using user buffer (not VBO) e.g. glVertexPointer
one thread could free memory before other thread used it.
Instead of copying this memory to driver simplier thing is
to block until draw finish.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
 2020-01-08 15:42:03 +00:00
Jason Ekstrand b788cccfe2 intel/disasm: Fix decoding of src0 of SENDS 
There is no instruction field for the register file for src0 because
it's always GRF.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3309>
 2020-01-08 14:14:16 +00:00
Yevhenii Kolesnikov 8dcff01c8b meta: Add cleanup function for Bitmap 
Buffer object and temporary texture were never freed, causing memory leaks.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
 2020-01-08 15:34:03 +02:00
Juan A. Suarez Romero ad4fb7ea04 nir/spirv: skip unreachable blocks in Phi second pass 
Only the blocks that are reachable are inserted with an end_nop
instruction at the end.

When handling the Phi second pass, if the Phi has a parent block that
does not have an end_nop then it means this block is unreachable, and
thus we can ignore it, as the Phi will never come through it.

Fixes dEQP-VK.graphicsfuzz.uninit-element-cast-in-loop.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
 2020-01-08 11:32:24 +01:00
Pierre-Eric Pelloux-Prayer 5f8daae4d8 radeonsi: check ctx->sdma_cs before using it 
e5167a9276 disabled SDMA for gfx8.
This caused 3 piglit arb_sparse_buffer tests (basic, buffer-data
and commit) to crash on GFX8.

Reported-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: e5167a9276 ("radeonsi: disable SDMA on gfx8 to fix corruption on RX 580")
 2020-01-08 09:31:35 +01:00
Samuel Pitoiset e565fd4255 radv: do not fill keys from fragment shader twice 
radv_fill_shader_info() already does that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2020-01-08 08:59:04 +01:00