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Author SHA1 Message Date
Alyssa Rosenzweig 6f3eea5ddb panfrost: Separate core ID range from core count 
To query the core count, the hardware has a SHADERS_PRESENT register containing
a mask of shader cores connected. The core count equals the number of 1-bits,
regardless of placement. This value is useful for public consumption (like
in clinfo).

However, internally we are interested in the range of core IDs.
We usually query core count to determine how many cores to allocate various
per-core buffers for (performance counters, occlusion queries, and the stack).
In each case, the hardware writes at the index of its core ID, so we have to
allocate enough for entire range of core IDs. If the core mask is
discontiguous, this necessarily overallocates.

Rename the existing core_count to core_id_range, better reflecting its
definition and purpose, and repurpose core_count for the actual core count.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17265>
 2022-07-08 01:14:55 +00:00
Alyssa Rosenzweig 5aa740bc8e pan/bi: Implement f2f16{_rtz, _rtne} 
Float conversions with explicit rounding modes are required for OpenCL,
as well as for Vulkan with the VK_KHR_16bit_storage extension (mandatory
in Vulkan 1.1). Since the hardware conversion instructions allow
configuring the round mode, this is easy to support :-)

Fixes test_half.vstore_half_rtz.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17262>
 2022-07-08 00:57:18 +00:00
Alyssa Rosenzweig 5f599fdef6 pan/va: Add missing <roundmode/> to V2F32_TO_V2F16 
So we can implement f2f16_rtz.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17262>
 2022-07-08 00:57:18 +00:00
Lionel Landwerlin 9680e0e4a2 intel/fs: ray query fix for global address 
With stages dispatching with a mask, we can run into situations where
we don't have the global address in all lanes. The existing code
always assumed we had the addres in at least lane0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: bb40e999d1 ("intel/nir: use a single intel intrinsic to deal with ray traversal")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17330>
 2022-07-08 00:36:04 +00:00
Alyssa Rosenzweig 9bd7570e96 pan/bi: Fix unpack_32_2x16 definition 
This got messed up when scalarizing the IR. Fix the definition of the opcode to
return (instead of break, asserting out) and to respect the swizzle (instead of
failing validation). Noticed when bringing up OpenCL on Valhall.

Fixes: 5febeae58e ("pan/bi: Emit collect and split")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17222>
 2022-07-07 23:16:39 +00:00
Jesse Natalie 6ee9002ff6 dzn: Fix winsys reporting 
For Windows we don't support using the DISPLAY winsys,
and for WSL we should add the ones that support software

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17346>
 2022-07-07 23:02:00 +00:00
Rhys Perry 48578713b7 radv,aco,ac/llvm: use nir_op_f{sin,cos}_amd 
This lets NIR optimize the multiplication, particularly sin/cos(a * #b).

fossil-db (Sienna Cichlid):
Totals from 12306 (7.58% of 162293) affected shaders:
MaxWaves: 224814 -> 224834 (+0.01%)
Instrs: 17365273 -> 17338758 (-0.15%); split: -0.16%, +0.00%
CodeSize: 93478488 -> 93354912 (-0.13%); split: -0.14%, +0.01%
VGPRs: 752080 -> 752072 (-0.00%); split: -0.00%, +0.00%
SpillSGPRs: 8440 -> 8410 (-0.36%)
Latency: 200402154 -> 200279405 (-0.06%); split: -0.06%, +0.00%
InvThroughput: 37588077 -> 37545545 (-0.11%); split: -0.11%, +0.00%
VClause: 293863 -> 293874 (+0.00%); split: -0.03%, +0.03%
SClause: 619539 -> 619064 (-0.08%); split: -0.09%, +0.01%
Copies: 1151591 -> 1151641 (+0.00%); split: -0.04%, +0.05%
Branches: 506434 -> 506437 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 877609 -> 877517 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 711938 -> 711940 (+0.00%); split: -0.00%, +0.00%

fossil-db (LLVM, Sienna Cichlid):
Totals from 4377 (3.59% of 121873) affected shaders:
SGPRs: 358960 -> 359176 (+0.06%); split: -0.18%, +0.25%
VGPRs: 319832 -> 319720 (-0.04%); split: -0.18%, +0.15%
SpillSGPRs: 46983 -> 47007 (+0.05%); split: -0.99%, +1.04%
CodeSize: 30872812 -> 30764512 (-0.35%); split: -0.39%, +0.04%
MaxWaves: 73814 -> 73904 (+0.12%); split: +0.25%, -0.13%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10587>
 2022-07-07 22:18:08 +00:00
Rhys Perry bb0415b697 nir: allow 16-bit fsin_amd/fcos_amd 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10587>
 2022-07-07 22:18:08 +00:00
Rhys Perry bc1ea2fda9 nir/algebraic: optimize bcsel(c, fsin/cos_amd(a), fsin/cos_amd(b)) 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10587>
 2022-07-07 22:18:08 +00:00
Rhys Perry 69d21a3dee nir: rename fsin_r600/fcos_r600 to fsin_amd/fcos_amd 
GCN has better range, but constant folding is the same.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10587>
 2022-07-07 22:18:08 +00:00
Pierre-Eric Pelloux-Prayer 835364ea0c vulkan/wsi: define pWaitDstStageMask in the blit submission 
Otherwise we get a crash in vk_common_QueueSubmit when doing:
   .stageMask   = pSubmits[s].pWaitDstStageMask[i],

cc: mesa-stable

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6712
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17310>
 2022-07-07 21:49:39 +00:00
Mike Blumenkrantz 3f11ae93be zink: support PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_FREEDRENO 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17189>
 2022-07-07 20:39:31 +00:00
Mike Blumenkrantz 2f46495ac0 zink: don't warn for missing customBorderColorWithoutFormat on turnip 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17189>
 2022-07-07 20:39:31 +00:00
Mike Blumenkrantz 6872adda26 zink: disable customBorderColorWithoutFormat on turnip 
this should "just work" now

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17189>
 2022-07-07 20:39:30 +00:00
Mike Blumenkrantz b6f23f4144 zink: init driver workarounds earlier in screen creation 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17189>
 2022-07-07 20:39:30 +00:00
Mike Blumenkrantz c4e18cd4dd mesa/st: add PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_FREEDRENO 
this is for drivers (like freedreno) which need the format in the sampler
state in order to accurately handle border colors

when set, drivers MAY receive a format in the sampler state if the frontend
supports it (e.g., nine does not), and the cso sampler cache will include
the format member of the struct

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17189>
 2022-07-07 20:39:30 +00:00
Mike Blumenkrantz ad0ee7ad42 mesa/st: make get_sampler_view_format() public 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17189>
 2022-07-07 20:39:30 +00:00
Kenneth Graunke ec2e8bc33f intel/compiler: Avoid copy propagating large registers into EOT messages 
EOT messages need to use g112-g127 for their sources.  With the new
opt_split_sends pass, we may be constructing an EOT message from two
different registers, and be able to copy propagate the original values
into those SENDs.

This can cause problems if we copy propagate from a large register
(say an RGBA value which is 4 GRFs in SIMD8 or 8 GRFs in SIMD16), in a
situation where the SEND only read a subset of that (say the alpha value
out of an RGBA texturing result).  g112-127 can only hold 16 registers
worth of data, and sometimes we can only use g112-126.  So, we can't
propagate if the GRFs in question are larger than 15 GRFs.

Fixes a shader validation failure in Alan Wake.  Thanks to Ian Romanick
for catching this!

shader-db on Icelake shows that only SIMD32 programs are affected, and
the results are pretty negligable:

   total instructions in shared programs: 19615228 -> 19615269 (<.01%)
   instructions in affected programs: 10702 -> 10743 (0.38%)
   helped: 1 / HURT: 43 / largest change: +/- 2 instructions

   total cycles in shared programs: 852001706 -> 852001566 (<.01%)
   cycles in affected programs: 767098 -> 766958 (-0.02%)
   helped: 68 / HURT: 64 / largest change: +/- 774 cycles

   GAINED: 2 / LOST: 0

Fixes: 589b03d02f ("intel/fs: Opportunistically split SEND message payloads")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6803
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17390>
 2022-07-07 20:20:01 +00:00
Gert Wollny 983385d319 r600/sfn: support nir_op_mulz and legazy math rules 
v2: Handle nir_op_ffmaz as well (Georg Lehmann)

Closes: #6390
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17076>
 2022-07-07 20:11:02 +00:00
Gert Wollny 9437cbb76d r600: Cleanup nir options 
A general cleanop of the nir compiler options including separating
the handling for FS and all the other shaders.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17076>
 2022-07-07 20:11:02 +00:00
Gert Wollny e562fde86a r600: enable sb by default also for NIR 
Currently, the NIR code path doesn't use clause local registers,
but these seem to help a lot with some work loads.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17076>
 2022-07-07 20:11:02 +00:00
Gert Wollny 79ca456b48 r600/sfn: rewrite NIR backend 
This is a rewite of the NIR backend. it adds some optimization
and a scheduler.

v2: - replace some magic numbers by constants
    - make sure constructor is always used with new
    - use default initialization in more places
      (changes suggested by Filip Gawin)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17076>
 2022-07-07 20:11:02 +00:00
Gert Wollny ab06b00c63 r600: Update nir options 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17076>
 2022-07-07 20:11:02 +00:00
Gert Wollny 3525d29a8d r600: Make sure that LDS instructions only use bank swizzle 012 
Not sure whether this is really needed. With the TGSI code path no
other bank swizzle is emitted for LDS ops, so make sure it's the same here.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17076>
 2022-07-07 20:11:01 +00:00
Gert Wollny 105b03a5ed r600: Add number of ALU groups to statistics 
The number of ALU groups is important for good sccheduling, so
let's add it to the stats.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17076>
 2022-07-07 20:11:01 +00:00
Lionel Landwerlin c67c9688c3 anv/utrace: use a bo pool for utrace buffers 
When utrace/perfetto is active, we allocate/free utrace buffers at the
same rate as command buffers. It's useful to have a pool that avoids
GEM_CREATE/GEM_CLOSE ioctls.

v2: Use the pool more

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16613>
 2022-07-07 18:49:05 +00:00
Jason Ekstrand 0b92636b62 dozen: Stop asking for semaphore/fence signaling 
Dozen is currently a SW driver as far as WSI is concerned so it's going
to wait on a fence anyway.  Also, I highly doubt it's actually hooked
these up properly.  It's probably just a copy+paste from ANV.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:20 -05:00
Jason Ekstrand 14dd5bd2cb dozen: Increase optimalBufferCopy*Alignment 
D3D12 requires the offset to be 512B-aligned and row pitch to be
256B-aligned for copy commands.  There will need to be a fallback
written eventually because Vulkan has no such requirements but these
will remain the optimal limits as they allow using the D3D12 copy
commands directly.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:19 -05:00
Jesse Natalie 8faf3781c8 vulkan/wsi/win32: Use the new helpers and persistent map 
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:19 -05:00
Jason Ekstrand aca545d616 vulkan/wsi/wayland: Use host pointer import when available 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:19 -05:00
Jason Ekstrand 54fa5ff406 vulkan/wsi/x11: Only use MIT_SHM if the device supports EXT_external_memory_host 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:19 -05:00
Jason Ekstrand 5abc05f1df vulkan/wsi/x11: Don't leak shm_reply if we don't have dri3 or present 
Fixes: b5c390c113 ("vulkan/wsi: add support for detecting mit-shm pixmaps.")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:19 -05:00
Jason Ekstrand 124848bf9e vulkan/wsi: Support tiled CPU images 
Some drivers such as lavapipe are 100% fine with using linear for WSI
images.  Most HW drivers, however, would rather render tiled and eat a
blit.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:19 -05:00
Jason Ekstrand 83fb6fe569 vulkan/wsi: Align buffer image strides to optimalBufferCopyRowPitchAlignment 
This isn't a big deal for the current buffer paths because the required
alignment for PRIME is already higher than any driver advertises.
However, the SW path we're about to add won't have the PRIME requirement.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:17 -05:00
Jason Ekstrand 13148b9c68 vulkan/wsi: Compute stride and size in configure_buffer_image 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:10 -05:00
Jason Ekstrand cf37837d36 vulkan/wsi: Persistently map CPU images 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 11:44:09 -05:00
Jason Ekstrand 1d0290fbfe vulkan/wsi: Delete SW support from configure_native_image 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 10:21:35 -05:00
Jason Ekstrand 4c79ec1934 vulkan/wsi/wayland: Use wsi_configure_cpu_image 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 10:21:34 -05:00
Jason Ekstrand 3d48b3c6f8 vulkan/wsi/x11: Use wsi_configure_cpu_image 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 10:21:33 -05:00
Jason Ekstrand afe2cb7b11 vulkan/wsi: Add a helper for creating CPU images 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 10:21:30 -05:00
Jason Ekstrand 1cc20fbefd vulkan/wsi: Move select_memory_type to common and rework it a bit 
Instead of taking a single boolean for device-local, take a set of
required properties and denied properties.  This will let us require
additional things like being CPU mappable in the future.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 10:21:29 -05:00
Jason Ekstrand fbb7b6e052 vulkan/wsi/wayland: Use a single memcpy in the SW path 
The strides match.  There's no reason to loop over image height.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 10:21:27 -05:00
Jason Ekstrand ca6bd57e76 vulkan/wsi: Pass the size to MapMemory in the SW path 
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17388>
 2022-07-07 10:21:24 -05:00
Tatsuyuki Ishi 2848e2f28e radv/ci: Move sample_texture.*_compressed_format_* to faillist for gfx<=9 
This turned out to be not a CTS bug but rather hardware bug around the
cache handle BCn textures.

It requires significant tracking to detect such cases, and it's likely
not worth a workaround since reading a texture as both compressed and
uncompressed in succession shall not be a realistic use case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6689
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17345>
 2022-07-07 13:19:56 +00:00
Pierre-Eric Pelloux-Prayer 5791826b1a mesa: skip draws with invalid indices offset 
It's easy to misuse glDrawElements and end up with an
invalid indices offset.
Since this can cause a hang, detect this case and skip
the draw.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6625
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662>
 2022-07-07 12:25:05 +00:00
Pierre-Eric Pelloux-Prayer 3c61f2cc15 util/blob: use memcpy in read functions 
Type casting may require specific alignment on some platforms;
since the input data can be provided by the application we can't
require any alignment.

Switch to using memcpy like the write functions do, and drop the
asserts.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6493
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662>
 2022-07-07 12:25:05 +00:00
Pierre-Eric Pelloux-Prayer 8856379a03 mesa/st: don't guess the internal format if it's known 
This fixes tests using imageLoad/imageStore on texture
created using glEGLImageTargetTexture2DOES.

Before this change, the format was guessed as GL_RGBA,
which would be rejected by _mesa_get_shader_image_format.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662>
 2022-07-07 12:25:05 +00:00
Pierre-Eric Pelloux-Prayer 085bdd89c2 dri: store internal_format when known 
For images created from textures or renderbuffer, the internal
format is known so store it.

This will be used in the next commit to replaces guessing it.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662>
 2022-07-07 12:25:05 +00:00
Lionel Landwerlin f1dd487531 intel/nir: temporarly disable opt_uniform_atomics for RT/CL 
Not had time to investiguate what is going is on but it's definitely a
contributor to failures.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16104>
 2022-07-07 10:21:48 +00:00
Gert Wollny bf29ebc0a7 virgl: Submit the TGSI_PROPERTY_SEPARABLE_PROGRAM when the host understands it 
We can't unconditionally support separable shader objects on the host,
so submit the property only if the shader is actually separable, the
host knows about the property, and supports SSO.

Without support for SSOs, the  host can still compile and link the shaders,
it needs to do more  work on interface matching though.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17344>
 2022-07-07 09:46:53 +00:00