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Author SHA1 Message Date
Rhys Perry 6872f8d861 aco/gfx11: allow true 16-bit instructions to access v128+ 
It looks like the LLVM assembler promotes true 16-bit instructions to VOP3
in this case.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
 2023-01-10 16:01:38 +00:00
Rhys Perry 254b178d5b aco: disallow SGPRS/constants with interpolation instructions 
https://reviews.llvm.org/D137575

The VINTRP format cannot encode anything except VGPRs.

Reading VINTERPInstructions.td, looks like it's the same for GFX11.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
 2023-01-10 16:01:38 +00:00
Rhys Perry 5af891a747 aco: add more opcodes to can_use_DPP() 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
 2023-01-10 16:01:38 +00:00
Rhys Perry c3dd1931d9 aco: allow Builder::Result to be dereferenced 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
 2023-01-10 16:01:38 +00:00
Rhys Perry e386523380 aco/gfx11: fix discard early exit removal optimization 
This optimization never happened because the NULL target was removed in
GFX11.

fossil-db (gfx1100):
Totals from 5439 (4.04% of 134574) affected shaders:
Instrs: 407865 -> 387123 (-5.09%)
CodeSize: 2163340 -> 2060644 (-4.75%)
Latency: 3432378 -> 3327802 (-3.05%)
InvThroughput: 270133 -> 262980 (-2.65%)
Branches: 8524 -> 3085 (-63.81%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20513>
 2023-01-10 14:01:29 +00:00
Pedro J. Estébanez 9d814c405b microsoft/spirv_to_dxil: Let linking report the need of runtime data 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20608>
 2023-01-10 13:43:01 +00:00
Lucas Stach 6481805e00 etnaviv: properly check for new clear value in sampler TS setup 
Comparing the 64bit clear value to the lower half 32bit clear state is
obviously wrong and results in a lot of false positives.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20586>
 2023-01-10 13:02:36 +00:00
Lucas Stach 03fdcbba19 etnaviv: blt: properly use upper half of clear value 
Instead of replicating the lower half of the clear value, properly
use the upper half to program the second clear value BLT state.

CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20586>
 2023-01-10 13:02:36 +00:00
Danylo Piliaiev a358890667 ir3/print: Consider the size of input when matching it to a reg 
First component of the input may never be read, so we have to find
the first component of the input which is being read.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20533>
 2023-01-10 12:37:19 +00:00
Danylo Piliaiev d474cc935e ir3: Force flat.b sources to be equal 
From cc29b940 according to Jonathan Marek using 2 immediates in a cat2
instruction is only "correct" if they are both equal.

They were not equal after reassigning of packed inlocks.

flat.b seemed to work fine even with imm values being different,
but better not to risk.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20533>
 2023-01-10 12:37:19 +00:00
Danylo Piliaiev a45d32b10b tu: Fix varyings interpolation reading stale values 
tu6_vpc_varying_mode returned how many bits are consumed IF they are
non-zero, for SMOOTH mode nothing is written and it was treated like
no bits were consumed.

When input with smooth interpolation was the last one and straddled
the VPC_VARYING_INTERP_MODE regs, the last interp mode were not written.

Fixes misrendering in "Psychonauts 2".

Cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20533>
 2023-01-10 12:37:19 +00:00
Michel Dänzer 25a151533c loader/dri3: Overhaul draw->cur_num_back handling 
draw->cur_num_back is no longer used for immediately reducing the number
of allocated back buffers. It just reflects how many of them are
currently allocated, and is used to prevent allocating more if the
current maximum is already reached.

This fixes an issue where the current in-progress back buffer could get
freed, which would result in visible artifacts.

Unused buffers are freed once they exceed buffer age 200. This ensures
we do not keep around more buffers than necessary in the long run.

v2:
* Drop buffer age threshold to 200. This will free unused buffers more
  quickly, and seems enough to avoid doing so prematurely even with
  "glxgears -fullscreen" running at thousands of frames per second.
* Use "buf_id != LOADER_DRI3_FRONT_ID". (Pierre-Eric Pelloux-Prayer)
* Simplify loader_dri3_get_buffers changes slightly.
* We can now use any unallocated back buffer slot in dri3_find_back.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20385>
 2023-01-10 10:44:17 +00:00
Michel Dänzer 27366cb510 loader/dri3: Add dri3_set_render_buffer helper 
Preparation for next commit, no functional change intended.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20385>
 2023-01-10 10:44:17 +00:00
Michel Dänzer 5d25a4cab4 loader/dri3: Move NULL handling into dri3_free_render_buffer 
Both checking for draw->buffers[buf_id] being non-NULL, and setting
draw->buffers[buf_id] = NULL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20385>
 2023-01-10 10:44:17 +00:00
Samuel Pitoiset 6e888f6159 radv: enable PS epilogs on-demand for some dynamic states 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>
 2023-01-10 09:55:29 +00:00
Samuel Pitoiset eb07a11b8f radv: add support for compiling PS epilogs on-demand 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>
 2023-01-10 09:55:29 +00:00
Samuel Pitoiset 11469f7553 radv: copy the non-compacted color format at pipeline bind time 
For PS epilogs on-demand.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>
 2023-01-10 09:55:29 +00:00
Samuel Pitoiset bbd7f70073 radv: rework PS epilog emission 
With PS epilogs compiled on-demand (for some dynamic states), they need
to be emitted outside of the graphics pipeline path. Also keep track
of the last emitted PS epilog to avoid redundant emission.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>
 2023-01-10 09:55:29 +00:00
Samuel Pitoiset 7de50e4c6c radv: keep track of SPI_SHADER_COL_FORMAT for PS epilogs 
To emit the related register.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>
 2023-01-10 09:55:29 +00:00
Samuel Pitoiset c9f30c4aa0 radv: enable the PS epilogs cache when some ds3 states are enabled 
These dynamic states need to compile PS epilogs on-demand.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>
 2023-01-10 09:55:29 +00:00
Samuel Pitoiset 75b0d6de04 radv: add support for a PS epilogs cache in the device 
Similar to VS prologs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20201>
 2023-01-10 09:55:29 +00:00
Eric Engestrom c0f95913a0 ci/rpi4: add a couple of tests as flaky 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20591>
 2023-01-10 09:03:28 +00:00
Eric Engestrom 7931b4026f ci/rpi3: add another test variant (draw-copypixels-sync) as flaky 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20591>
 2023-01-10 09:03:28 +00:00
Erik Faye-Lund 28d6caad60 gallium/draw: assert shader-stage 
Nobody calls this for the wrong shader-stage. Let's turn that check into
an assert instead.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20096>
 2023-01-10 08:22:17 +00:00
Erik Faye-Lund 7c1b9ee6b7 gallium/draw: use nir_shader_instructions_pass for nir_lower_aaline_fs 
This just cuts away some needless boilerplate code.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20096>
 2023-01-10 08:22:17 +00:00
Samuel Pitoiset 3897a233fb radv: add a new dirty flag for the RB+ state 
With PS epilogs on-demand, the non-compacted color format field won't
come from the pipeline and it seems easier to introduce a new dirty
flag for re-emitting this state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18552>
 2023-01-10 07:59:33 +00:00
Yiwei Zhang f1e06b46a9 lvp: avoid redundant sampler views and image views 
Align the sampler view creation condition with the image and buffer
creation usage which maps to PIPE_BIND_SAMPLER_VIEW, which fixes the spam
of "Illegal sampler view creation without bind flag". Also fix the
PIPE_BIND_SHADER_IMAGE assignment for image usage bits and avoid setting
the image view struct if without PIPE_BIND_SHADER_IMAGE.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20580>
 2023-01-10 05:49:34 +00:00
Mike Blumenkrantz f18827e015 zink: stop using VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT 
this used to be fine back when there was only one thread doing cache management,
but now the cache is used by precompile threads too, so let the driver do sync

fixes #7660

Fixes: 41ffb15de5 ("zink: implement async gfx precompile")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20519>
 2023-01-10 05:33:10 +00:00
Alyssa Rosenzweig 2e9ac9278c agx: Remove obsolete comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>
 2023-01-10 05:19:25 +00:00
Alyssa Rosenzweig 90dea84ef6 agx: Remove dead arg 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>
 2023-01-10 05:19:25 +00:00
Alyssa Rosenzweig 17d1559036 agx: Use i0/i1 variables 
Now that we've defined them.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>
 2023-01-10 05:19:25 +00:00
Alyssa Rosenzweig 1e61f13ffd agx: Get rid of emit_alu_bool 
Deduplicate lots of cases. Splitting this out was silly, bools aren't that
special.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>
 2023-01-10 05:19:25 +00:00
Alyssa Rosenzweig 5b25ee6cc7 agx: Use agx_subdivide_to for umul_high 
Helpers!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>
 2023-01-10 05:19:25 +00:00
Alyssa Rosenzweig f6c5b2a5a3 agx: Remove dead code 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20559>
 2023-01-10 05:19:25 +00:00
Dmitry Osipenko dd571ede85 docs/envvars: Document MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ 
Add documentation for the MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ environment
variable.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Juston Li <justonli@google.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20595>
 2023-01-10 04:53:44 +00:00
Dmitry Osipenko 6c1c5d9ef0 util/disk_cache: Fix rw cache lookup when using combined ro+rw caches 
When combining of ro+rw caches is enabled, at first the ro cache should be
looked up and if data isn't found there then rw cache should be checked.
The rw cache checking got lost by accident after the code rebase and there
was no unit test covering this condition. Fix the rw cache looking up and
add the unit test case.

Fixes: 32fe60e8c4 ("util/disk_cache: Support combined foz ro and non-foz rw caches")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Juston Li <justonli@google.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20595>
 2023-01-10 04:53:44 +00:00
Jesse Natalie 8b79e6fb5e dzn: No need to add another bind flag for clears if one is already present 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie c59141d3c2 dzn: Lower tg4 offsets 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie 9a991cc52e dzn: Implement point coord 
Since we don't support wide points, this isn't a useful feature, but the CTS
requires a particular point coord value for the single rasterized pixel, based
on where the original point coord fell within the pixel. Since we're not doing
a quad, we don't get free interpolation like the GL driver does, so split the
logic between vertex (transform point center into screen space) and pixel
(compute delta between current pixel/sample and point center).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie 03ce60ec7e dzn: Lower fragcoord wtrans 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie e8b12006bb dzn: Use the right variable for heap slots when prepping resolves 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie 22b8e0c74c microsoft/compiler: Set the advanced texture ops flag correctly 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie a84208ee4d microsoft/compiler: Fill out and sort the shader/module flags 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie beeeb74a4c microsoft/compiler: For Vulkan, centroid should be ignored on position 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie d3cae18cb5 microsoft/compiler: For Vulkan, when shading at sample rate, pos is sample pos 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Jesse Natalie b0f3a387c9 nir_lower_fragcoord_wtrans: Support Vulkan shaders 
In Vulkan shaders, you might not have all derefs pointing to a variable

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20400>
 2023-01-10 04:25:26 +00:00
Timothy Arceri ac5af6c06d util/driconf: add Dune: Spice Wars workaround 
As per the bug report the game does not correctly handle a uniform
index of -1 being returned for the unused array element, which
results in rendering issues. So here we skip the uniform array
resizing optimisation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6397
Cc: mesa-stable

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20579>
 2023-01-10 03:53:19 +00:00
Giancarlo Devich e986d8c337 d3d12: Update hard-coded heap sizes and batch limit 
Increasing the heap sizes and active batch count reduces flushing
churn when rendering runs out of descriptors.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20589>
 2023-01-10 03:22:26 +00:00
Daniel Stone 9c1fbc076a Return 'Mesa' for GL_VENDOR for community drivers 
Rather than a grab-bag of random values, return 'Mesa' as the GL_VENDOR
string for all community-supported drivers.

Drivers which are primarily developed/maintained by the hardware vendor
retain that vendor's name as the GL_VENDOR string.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16064>
 2023-01-10 01:50:33 +00:00
WebsterEndymion 7d9eb64990 zink: fix the stencil write 
Stencil writing also needs to be considered when setting the flag renderpass

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20245>
 2023-01-10 01:30:02 +00:00