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11389 Commits

Author SHA1 Message Date
Caio Oliveira 625338389e intel/brw: Update comments for FK macro 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 4e16c565f4 intel/brw: Remove Gfx8- code from inst FFDC, FDC and FD macros 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira b2822bc8d4 intel/brw: Remove Gfx8- code from inst BRW_IA*_ADDR_IMM macros 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira a7da7e4e69 intel/brw: Remove Gfx8- code from inst FI macros 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 7b523a9f8e intel/brw: Remove Gfx8- code from inst FD20 and FV20 macros 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira e684ab6a06 intel/brw: Remove Gfx8- code from inst F20 macros 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 72a73eca96 intel/brw: Replace inst F8 macro with F macro 
F8 had a case for 4+, 8+ and 12+.  Its uses now can be replaced
with F that has a case for 9+ and 12+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira add6ea8a22 intel/brw: Remove Gfx8- code from inst FC and F macros 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira ccece38623 intel/brw: Remove Gfx8- specific EU inst helpers 
The "generic" macros will be handled in a separate patch.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira e8ee44e8f1 intel/brw: Remove Gfx8- code from register type helpers 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 0a637dce05 intel/brw: Remove Gfx8- code from NIR options 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira d61d6fc3bc intel/brw: Remove Gfx8- code from EU codegen helpers 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 99d41ca90d intel/brw: Remove Gfx4-5 manual compression selection 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira a1e694a890 intel/brw: Remove Gfx8- code from NIR passes 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 99f173ddd2 intel/brw: Remove Gfx8- code from EU validation 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira f321e555b6 intel/brw: Remove Gfx8- code from EU emission 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 91c05d990a intel/brw: Remove Gfx8- code from IR performance analysis 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 5765c7b80c intel/brw: Remove Gfx8- code from EU compaction 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 7ac5696157 intel/brw: Remove Gfx8- code from backend passes 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 9569ea82a8 intel/brw: Remove Gfx8- code from generator 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 371468c013 intel/brw: Remove Gfx8- code from lower logical sends 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 1ee29f82d2 intel/brw: Remove Gfx8- code from lower storage image pass 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 6a03280af1 intel/brw: Remove Gfx8- code from NIR conversion 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 2a1c2a1bf1 intel/brw: Remove Gfx8- code from thread payload 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira ed6f0665e0 intel/brw: Remove Gfx8- code from register allocator 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 85eb672325 intel/brw: Remove Gfx8- code from scheduler 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 6e88fa8a77 intel/brw: Remove Gfx8- code from brw_compile_* functions 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira a4bf016582 intel/brw: Remove Gfx8- code from assembler 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 83d7ddebcb intel/brw: Remove Gfx8- code from disassembler 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira 15469b0a63 intel/brw: Remove unused legacy shader stages 
CLIP, STRIP-FAN and FF Geometry don't apply to Gfx9+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira c621f75e7b intel/brw: Remove now unused vec4-only opcodes 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:38 +00:00
Caio Oliveira a641aa294e intel/brw: Remove vec4 backend 
It still exists as part of ELK for older gfx versions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:37 +00:00
Caio Oliveira 7c23b90537 intel/brw: Always use scalar shaders 
Remove scalar_stage[] array, since now it is always scalar.  This
removes any usage of vec4 shaders in brw.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:37 +00:00
Caio Oliveira 303fd4e935 intel/brw: Move type_size_* functions out of vec4-specific file 
Will make easier later to delete vec4 files.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:37 +00:00
Caio Oliveira 9bfccc1935 intel/brw: Move brw_compile_* functions out of vec4-specific files 
These contain code that is both fs and vec4.  Will make easier later to
delete vec4 files.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:37 +00:00
Caio Oliveira c11d7743b3 intel/blorp: Remove Gfx8- references in BRW code 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
 2024-02-28 05:45:37 +00:00
Vinson Lee 6c190bdfe9 intel/clc: Fix file descriptor leak 
Fix defect reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable fp going out of scope leaks the storage it points to.

Fixes: 4fd7495c69 ("intel/clc: add ability to output NIR")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27778>
 2024-02-28 04:30:33 +00:00
Faith Ekstrand c09c086c12 vulkan: Add a vk_render_pass_state_has_attachment_info() helper 
We already have a helper like this internally.  Give it a better name
and expose it.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27024>
 2024-02-27 22:17:09 +00:00
Ian Romanick 535caaf3e0 nir: Optimize uniform iadd, fadd, and ixor reduction operations 
This adds optimizations for iadd, fadd, and ixor with reduce,
inclusive scan, and exclusive scan.

NOTE: The fadd and ixor optimizations had no shader-db or fossil-db
changes on any Intel platform.

NOTE 2: This change "fixes" arb_compute_variable_group_size-local-size
and base-local-size.shader_test on DG2 and MTL. This is just changing
the code path taken to not use whatever path was not working properly
before.

This is a subset of the things optimized by ACO. See also
https://gitlab.freedesktop.org/mesa/mesa/-/issues/3731#note_682802. The
min, max, iand, and ior exclusive_scan optimizations are not
implemented.

Broadwell on shader-db is not happy. I have not investigated.

v2: Silence some warnings about discarding const.

v3: Rename mbcnt to count_active_invocations. Add a big comment
explaining the differences between the two paths. Suggested by Rhys.

shader-db:

All Gfx9 and newer platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20300384 -> 20299545 (<.01%)
instructions in affected programs: 19167 -> 18328 (-4.38%)
helped: 35 / HURT: 0

total cycles in shared programs: 842809750 -> 842766381 (<.01%)
cycles in affected programs: 2160249 -> 2116880 (-2.01%)
helped: 33 / HURT: 2

total spills in shared programs: 4632 -> 4626 (-0.13%)
spills in affected programs: 206 -> 200 (-2.91%)
helped: 3 / HURT: 0

total fills in shared programs: 5594 -> 5581 (-0.23%)
fills in affected programs: 664 -> 651 (-1.96%)
helped: 3 / HURT: 1

fossil-db results:

All Intel platforms had similar results. (Ice Lake shown)
Totals:
Instrs: 165551893 -> 165513303 (-0.02%)
Cycles: 15132539132 -> 15125314947 (-0.05%); split: -0.05%, +0.00%
Spill count: 45258 -> 45204 (-0.12%)
Fill count: 74286 -> 74157 (-0.17%)
Scratch Memory Size: 2467840 -> 2451456 (-0.66%)

Totals from 712 (0.11% of 656120) affected shaders:
Instrs: 598931 -> 560341 (-6.44%)
Cycles: 184650167 -> 177425982 (-3.91%); split: -3.95%, +0.04%
Spill count: 983 -> 929 (-5.49%)
Fill count: 2274 -> 2145 (-5.67%)
Scratch Memory Size: 52224 -> 35840 (-31.37%)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27044>
 2024-02-27 09:44:11 -08:00
Ian Romanick c63ea755fe intel/fs: Use nir_opt_uniform_subgroup 
shader-db:

All Skylake and newer platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20300435 -> 20300384 (<.01%)
instructions in affected programs: 303 -> 252 (-16.83%)
helped: 2 / HURT: 0

total cycles in shared programs: 842810326 -> 842809750 (<.01%)
cycles in affected programs: 8374 -> 7798 (-6.88%)
helped: 2 / HURT: 0

fossil-db:

All Intel platforms (note below) had similar results. (Ice Lake shown)
Instrs: 165559735 -> 165551893 (-0.00%)
Cycles: 15133083961 -> 15132539132 (-0.00%); split: -0.00%, +0.00%
Spill count: 45262 -> 45258 (-0.01%)
Fill count: 74293 -> 74286 (-0.01%)

Totals from 854 (0.13% of 656120) affected shaders:
Instrs: 3461998 -> 3454156 (-0.23%)
Cycles: 154252729 -> 153707900 (-0.35%); split: -0.36%, +0.01%
Spill count: 2655 -> 2651 (-0.15%)
Fill count: 3881 -> 3874 (-0.18%)

DG2 did not see changes in spills or fills.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27044>
 2024-02-27 08:38:45 -08:00
Ian Romanick 8fb37ef985 intel/fs: Add fast path for ballot(true) 
This doesn't help very much now. A later commit adds a NIR optimization
pass, tentatively called nir_opt_uniform_subgroup, that converts many
kinds of subgroup operations to things involving
bitCount(ballot(true)). This commit makes a huge difference in the
results of that later commit.

No shader-db changes on any Intel platform.

Fossil-db results:

All Intel platforms had similar results. (Ice Lake shown)
Totals:
Instrs: 165558033 -> 165557519 (-0.00%)
Cycles: 15156188362 -> 15156178922 (-0.00%); split: -0.00%, +0.00%

Totals from 299 (0.05% of 656117) affected shaders:
Instrs: 88293 -> 87779 (-0.58%)
Cycles: 3709498 -> 3700058 (-0.25%); split: -0.28%, +0.03%

v2: Rebase on splitting ELK from BRW. Remove devinfo->ver >= 8 check.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27044>
 2024-02-27 08:37:46 -08:00
Ian Romanick c42830c64a intel/fs: Use constant of same type to write flag 
Otherwise the compiler generates an extra MOV to load the constant into
a register first because reasons. 🤷 vote_any, vote_all, vote_ieq,
and vote_feq handling already do this.

No shader-db changes on any Intel plaform.

Fossil-db results:

All Intel platforms had similar results. (Ice Lake shown)
Totals:
Instrs: 165592451 -> 165557937 (-0.02%)
Cycles: 15133282615 -> 15133059360 (-0.00%); split: -0.00%, +0.00%

Totals from 33779 (5.15% of 656115) affected shaders:
Instrs: 4396576 -> 4362062 (-0.79%)
Cycles: 86867412 -> 86644157 (-0.26%); split: -0.37%, +0.11%

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27044>
 2024-02-27 08:37:15 -08:00
Ian Romanick b22fff90d5 intel/fs: Enable nir_opt_uniform_atomics in all shader stages 
The problem seems to have been related to
nir_intrinsic_load_global_block_intel being marked as non-divergent.

No shader-db or fossil-db changes on any Intel platform.

v2: Rebase on splitting ELK from BRW. Remove devinfo->ver >= 8 check.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27044>
 2024-02-27 08:37:05 -08:00
Ian Romanick 56a3f031f4 intel/fs: Delete stale comment in nir_intrinsic_ballot implementation 
Discard actually uses f1.x, so this implementation of ballot is fine.

Trivial.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27044>
 2024-02-27 08:36:34 -08:00
José Roberto de Souza 90e38bbb3b intel/tools/error_decode: Parse Xe KMD error dump file 
There is more to do but this is able to parse batch buffers, including
fetch and parse other bos like shader programs.

Some functions used by read_i915_data_file() could be shared with Xe
so I have moved those to aubinator_error_decode_lib.c/h.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27661>
 2024-02-27 01:04:16 +00:00
José Roberto de Souza 7e88176b0b intel/tools/error_decode: Move code that can be shared between i915 and Xe error decoders 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27661>
 2024-02-27 01:04:16 +00:00
José Roberto de Souza c26663eede anv/xe: Add VMs to error dump 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27661>
 2024-02-27 01:04:15 +00:00
Sagar Ghuge 5e800ab6f7 anv: Implement VK_AMD_texture_gather_bias_lod 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>
 2024-02-27 00:22:46 +00:00
Sagar Ghuge 269d2c4a3f intel/compiler: Enable packing of offset with LOD or Bias 
Move intel_nir_lower_texture just before nir_lower_tex since we need to
operate on the offset and those are getting lowerd.

v2: (Ian)
- Rename variable name to intel_tex_options

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>
 2024-02-27 00:22:46 +00:00
Sagar Ghuge 6f0ab5e4d5 intel/compiler: Add texture gather offset LOD/Bias message support 
v2: (Ian)
- Space formatting on conditional statement

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>
 2024-02-27 00:22:46 +00:00