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intel/brw: Remove now unused vec4-only opcodes

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
This commit is contained in:
Caio Oliveira
2024-02-14 23:50:02 -08:00
committed by Marge Bot
parent a641aa294e
commit c621f75e7b
5 changed files with 0 additions and 161 deletions
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src/intel/compiler/brw_eu_defines.h
-39
View File
@@ -397,11 +397,8 @@ enum opcode {
* Source 4: [required] Opcode-specific control immediate, same as source 2
* of the matching non-LOGICAL opcode.
*/
VEC4_OPCODE_UNTYPED_ATOMIC,
SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
VEC4_OPCODE_UNTYPED_SURFACE_READ,
SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
@@ -553,20 +550,6 @@ enum opcode {
*/
SHADER_OPCODE_HALT_TARGET,
VEC4_OPCODE_MOV_BYTES,
VEC4_OPCODE_PACK_BYTES,
VEC4_OPCODE_UNPACK_UNIFORM,
VEC4_OPCODE_DOUBLE_TO_F32,
VEC4_OPCODE_DOUBLE_TO_D32,
VEC4_OPCODE_DOUBLE_TO_U32,
VEC4_OPCODE_TO_DOUBLE,
VEC4_OPCODE_PICK_LOW_32BIT,
VEC4_OPCODE_PICK_HIGH_32BIT,
VEC4_OPCODE_SET_LOW_32BIT,
VEC4_OPCODE_SET_HIGH_32BIT,
VEC4_OPCODE_MOV_FOR_SCRATCH,
VEC4_OPCODE_ZERO_OOB_PUSH_REGS,
FS_OPCODE_DDX_COARSE,
FS_OPCODE_DDX_FINE,
/**
@@ -586,29 +569,11 @@ enum opcode {
FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
VEC4_VS_OPCODE_URB_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GFX7,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
/**
* Write geometry shader output data to the URB.
*
* Unlike VEC4_VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
* R0 to the first MRF. This allows the geometry shader to override the
* "Slot {0,1} Offset" fields in the message header.
*/
VEC4_GS_OPCODE_URB_WRITE,
/**
* Write geometry shader output data to the URB and request a new URB
* handle (gfx6).
*
* This opcode doesn't do an implied move from R0 to the first MRF.
*/
VEC4_GS_OPCODE_URB_WRITE_ALLOCATE,
/**
* Terminate the geometry shader thread by doing an empty URB write.
*
@@ -779,11 +744,7 @@ enum opcode {
/** Fills out a relocatable immediate */
SHADER_OPCODE_MOV_RELOC_IMM,
VEC4_OPCODE_URB_READ,
TCS_OPCODE_GET_INSTANCE_ID,
VEC4_TCS_OPCODE_URB_WRITE,
VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS,
VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
TCS_OPCODE_GET_PRIMITIVE_ID,
TCS_OPCODE_CREATE_BARRIER_HEADER,
TCS_OPCODE_SRC0_010_IS_ZERO,
src/intel/compiler/brw_fs.cpp
-3
View File
@@ -295,9 +295,6 @@ fs_inst::is_payload(unsigned arg) const
switch (opcode) {
case FS_OPCODE_FB_WRITE:
case FS_OPCODE_FB_READ:
case VEC4_OPCODE_UNTYPED_ATOMIC:
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
src/intel/compiler/brw_ir_performance.cpp
-55
View File
@@ -317,17 +317,6 @@ namespace {
case FS_OPCODE_PIXEL_X:
case FS_OPCODE_PIXEL_Y:
case FS_OPCODE_SET_SAMPLE_ID:
case VEC4_OPCODE_MOV_BYTES:
case VEC4_OPCODE_UNPACK_UNIFORM:
case VEC4_OPCODE_DOUBLE_TO_F32:
case VEC4_OPCODE_DOUBLE_TO_D32:
case VEC4_OPCODE_DOUBLE_TO_U32:
case VEC4_OPCODE_TO_DOUBLE:
case VEC4_OPCODE_PICK_LOW_32BIT:
case VEC4_OPCODE_PICK_HIGH_32BIT:
case VEC4_OPCODE_SET_LOW_32BIT:
case VEC4_OPCODE_SET_HIGH_32BIT:
case VEC4_OPCODE_ZERO_OOB_PUSH_REGS:
case GS_OPCODE_SET_DWORD_2:
case GS_OPCODE_SET_WRITE_OFFSET:
case GS_OPCODE_SET_VERTEX_COUNT:
@@ -364,7 +353,6 @@ namespace {
case BRW_OPCODE_ADD3:
case BRW_OPCODE_MUL:
case SHADER_OPCODE_MOV_RELOC_IMM:
case VEC4_OPCODE_MOV_FOR_SCRATCH:
if (devinfo->ver >= 11) {
return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2,
0, 10, 6, 14, 0, 0);
@@ -830,27 +818,8 @@ namespace {
else
abort();
case VEC4_OPCODE_PACK_BYTES:
if (devinfo->ver >= 8)
return calculate_desc(info, EU_UNIT_FPU, 4 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */,
0, 0);
else if (devinfo->verx10 >= 75)
return calculate_desc(info, EU_UNIT_FPU, 4 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 10 /* XXX */, 6 /* XXX */, 16 /* XXX */,
0, 0);
else
return calculate_desc(info, EU_UNIT_FPU, 4 /* XXX */, 0, 0,
4 /* XXX */, 0,
0, 12 /* XXX */, 8 /* XXX */, 18 /* XXX */,
0, 0);
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
case TCS_OPCODE_GET_INSTANCE_ID:
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
if (devinfo->ver >= 8)
return calculate_desc(info, EU_UNIT_FPU, 22 /* XXX */, 0, 0,
@@ -934,13 +903,8 @@ namespace {
8 /* XXX */, 750 /* XXX */, 0, 0,
2 /* XXX */, 0);
case VEC4_OPCODE_URB_READ:
case VEC4_VS_OPCODE_URB_WRITE:
case VEC4_GS_OPCODE_URB_WRITE:
case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
case GS_OPCODE_THREAD_END:
case GS_OPCODE_FF_SYNC:
case VEC4_TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
case TCS_OPCODE_THREAD_END:
return calculate_desc(info, EU_UNIT_URB, 2, 0, 0, 0, 6 /* XXX */,
@@ -978,25 +942,6 @@ namespace {
return calculate_desc(info, EU_UNIT_DP_DC, 2, 0, 0, 0, 8 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0, 0, 0);
case VEC4_OPCODE_UNTYPED_ATOMIC:
if (devinfo->ver >= 7)
return calculate_desc(info, EU_UNIT_DP_DC, 2, 0, 0,
30 /* XXX */, 400 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0,
0, 400 /* XXX */);
else
abort();
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
if (devinfo->ver >= 7)
return calculate_desc(info, EU_UNIT_DP_DC, 2, 0, 0,
0, 20 /* XXX */,
10 /* XXX */, 100 /* XXX */, 0, 0,
0, 0);
else
abort();
case FS_OPCODE_FB_WRITE:
case FS_OPCODE_FB_READ:
case FS_OPCODE_REP_FB_WRITE:
src/intel/compiler/brw_schedule_instructions.cpp
-11
View File
@@ -402,17 +402,6 @@ schedule_node::set_latency_gfx7(const struct brw_isa_info *isa)
latency = 50;
break;
case VEC4_OPCODE_UNTYPED_ATOMIC:
/* See GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP */
latency = 14000;
break;
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
/* See also GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ */
latency = is_haswell ? 300 : 600;
break;
case SHADER_OPCODE_SEND:
switch (inst->sfid) {
case BRW_SFID_SAMPLER: {
src/intel/compiler/brw_shader.cpp
-53
View File
@@ -297,16 +297,10 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
return "image_size_logical";
case VEC4_OPCODE_UNTYPED_ATOMIC:
return "untyped_atomic";
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
return "untyped_atomic_logical";
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
return "untyped_surface_read";
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
return "untyped_surface_read_logical";
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
return "untyped_surface_write";
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
return "untyped_surface_write_logical";
case SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
@@ -394,33 +388,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
case SHADER_OPCODE_GET_BUFFER_SIZE:
return "get_buffer_size";
case VEC4_OPCODE_MOV_BYTES:
return "mov_bytes";
case VEC4_OPCODE_PACK_BYTES:
return "pack_bytes";
case VEC4_OPCODE_UNPACK_UNIFORM:
return "unpack_uniform";
case VEC4_OPCODE_DOUBLE_TO_F32:
return "double_to_f32";
case VEC4_OPCODE_DOUBLE_TO_D32:
return "double_to_d32";
case VEC4_OPCODE_DOUBLE_TO_U32:
return "double_to_u32";
case VEC4_OPCODE_TO_DOUBLE:
return "single_to_double";
case VEC4_OPCODE_PICK_LOW_32BIT:
return "pick_low_32bit";
case VEC4_OPCODE_PICK_HIGH_32BIT:
return "pick_high_32bit";
case VEC4_OPCODE_SET_LOW_32BIT:
return "set_low_32bit";
case VEC4_OPCODE_SET_HIGH_32BIT:
return "set_high_32bit";
case VEC4_OPCODE_MOV_FOR_SCRATCH:
return "mov_for_scratch";
case VEC4_OPCODE_ZERO_OOB_PUSH_REGS:
return "zero_oob_push_regs";
case FS_OPCODE_DDX_COARSE:
return "ddx_coarse";
case FS_OPCODE_DDX_FINE:
@@ -461,8 +428,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
return "interp_per_slot_offset";
case VEC4_VS_OPCODE_URB_WRITE:
return "vs_urb_write";
case VS_OPCODE_PULL_CONSTANT_LOAD:
return "pull_constant_load";
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
@@ -471,10 +436,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
return "unpack_flags_simd4x2";
case VEC4_GS_OPCODE_URB_WRITE:
return "gs_urb_write";
case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
return "gs_urb_write_allocate";
case GS_OPCODE_THREAD_END:
return "gs_thread_end";
case GS_OPCODE_SET_WRITE_OFFSET:
@@ -514,16 +475,8 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
case SHADER_OPCODE_MOV_RELOC_IMM:
return "mov_reloc_imm";
case VEC4_OPCODE_URB_READ:
return "urb_read";
case TCS_OPCODE_GET_INSTANCE_ID:
return "tcs_get_instance_id";
case VEC4_TCS_OPCODE_URB_WRITE:
return "tcs_urb_write";
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
return "tcs_set_input_urb_offsets";
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
return "tcs_set_output_urb_offsets";
case TCS_OPCODE_GET_PRIMITIVE_ID:
return "tcs_get_primitive_id";
case TCS_OPCODE_CREATE_BARRIER_HEADER:
@@ -1105,10 +1058,8 @@ backend_instruction::has_side_effects() const
return send_has_side_effects;
case BRW_OPCODE_SYNC:
case VEC4_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
@@ -1124,7 +1075,6 @@ backend_instruction::has_side_effects() const
case FS_OPCODE_FB_WRITE_LOGICAL:
case FS_OPCODE_REP_FB_WRITE:
case SHADER_OPCODE_BARRIER:
case VEC4_TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
case SHADER_OPCODE_RND_MODE:
case SHADER_OPCODE_FLOAT_CONTROL_MODE:
@@ -1134,7 +1084,6 @@ backend_instruction::has_side_effects() const
case SHADER_OPCODE_BTD_SPAWN_LOGICAL:
case SHADER_OPCODE_BTD_RETIRE_LOGICAL:
case RT_OPCODE_TRACE_RAY_LOGICAL:
case VEC4_OPCODE_ZERO_OOB_PUSH_REGS:
return true;
default:
return eot;
@@ -1148,14 +1097,12 @@ backend_instruction::is_volatile() const
case SHADER_OPCODE_SEND:
return send_is_volatile;
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
case VEC4_OPCODE_URB_READ:
return true;
default:
return false;