6deb1950a4
anv: Update RT dispatch globals to use 64bit data structure
...
Rework (Kevin)
- Fix Hit/Miss/Resume shader group table value
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047 >
2025-04-21 20:10:45 +00:00
fcd5fe4a75
intel/genxml/xe3: Update 3STATE_BTD field
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047 >
2025-04-21 20:10:45 +00:00
a96e280dfe
intel: Program XY_FAST_COLOR_BLT::Destination Mocs for gfx12
...
Copy engine is not used in gfx12 platforms on ANV but that is possible
in Iris.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34560 >
2025-04-17 18:11:44 +00:00
4ac900b5bf
anv/genxml: use special genX video pack files
...
Before:
30453 ./build/src/intel/genxml/gen125_pack.h
After:
17026 ./build/src/intel/genxml/gen125_pack.h
21589 ./build/src/intel/genxml/gen125_video_pack.h
The idea is to have fewer line to parse in each genX_*.c file.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276 >
2025-04-01 00:03:56 +03:00
4fdf5618f9
intel/genxml: add MI_FLUSH_DW to blitter engine
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276 >
2025-04-01 00:03:53 +03:00
79a463e40b
intel/genxml: define post-sync operations for MI_FLUSH_DW
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276 >
2025-04-01 00:03:50 +03:00
d4899b0486
intel/genxml: fixup engine filtering
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276 >
2025-04-01 00:03:47 +03:00
04b6eeba63
intel/genxml: add more engine tagging on instructions
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276 >
2025-04-01 00:03:42 +03:00
891965a471
intel/genxml: remove ISA fields
...
Those are for the compiler afaict.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276 >
2025-04-01 00:03:07 +03:00
c6757cb8f0
isl: enable CPB compression
...
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10760
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20741 >
2025-03-28 04:38:09 +00:00
02eb26de0a
genxml: simplify genX_rt_pack.h
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751 >
2025-03-05 17:20:11 +00:00
374d2168ee
intel/genxml: add a genX RT include header
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751 >
2025-03-05 17:20:11 +00:00
723e52cbcc
anv: Support putting image base address and image params in surface state
...
images params including pitch, width, height and tile mode
for image address caculation
Signed-off-by: Mi, Yanfeng <yanfeng.mi@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32676 >
2025-02-23 15:16:51 +00:00
49bc323866
intel: Fix typos
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33556 >
2025-02-15 17:43:44 +00:00
2a8dddb519
genxml: add convenience dwords for packing components
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32418 >
2025-02-13 14:36:15 +00:00
e40f47abd3
genxml: make component packing an array
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32418 >
2025-02-13 14:36:15 +00:00
efeeae3926
intel/genxml: Update BLEND_STATE_ENTRY structure
...
This change adds the SimpleFloatBlendEnable field to the structure.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32739 >
2025-02-05 22:27:54 -08:00
4e80045ae0
intel/genxml/anv: fix the layout of call stack handler struct
...
Patch adds new CALL_STACK_HANDLER struct which has offset to
start and end of RegistersPerThread field, this spec changes is
described in Wa_22019854901 (see HSD 22019967134).
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33342 >
2025-02-04 08:44:04 +00:00
dd1712515b
anv/xe3+: Set RegistersPerThread for bindless shader dispatch.
...
v2: Use MOV and wrap in conditional during BTD spawn header setup
(Lionel). Remove references to SIMD8 (Tapani).
v3: Update brw_bsr() to specify number of registers per thread, don't
initialize Registers Per Thread on BTD spawn header (Lionel).
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664 >
2025-01-29 23:39:32 +00:00
f6a1c51de7
intel/genxml/xe3+: Update definitions for shader state setup.
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32664 >
2025-01-29 23:39:32 +00:00
db11165c07
intel/cl: switch to SPIRV as shader storage
...
Effectively making intel-clc not needed.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Dylan Baker <dylan@pnwbakers.com >
Tested-by: Matt Turner <mattst88@gmail.com >
Reviewed-by: Dylan Baker <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33014 >
2025-01-25 03:28:07 +00:00
3f3d6c04a3
intel/genxml: define MEMORYADDRESSATTRIBUTES for Gen12.5 with TILEF
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32775 >
2025-01-10 21:45:04 +00:00
68477ae7c0
genxml: add av1 fields
...
Co-authored-by: Hyunjun Ko <zzoon@igalia.com >
- Remove HuC pipeline params of VD_PIPELINE_FLUSH
- Fix length of AVP_PIPE_MODE_SELECT, AVP_PIC_STATE, AVP_PIPE_BUF_ADDR_STATE
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32775 >
2025-01-10 21:45:04 +00:00
0bca8da981
intel/genxml: Update URB related instructions and structures
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736 >
2025-01-09 21:26:40 +00:00
9d33443d7b
intel/genxml: Add coarse pixel related changes
...
This change adds CPS related new state instruction, structure and
enum.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32737 >
2025-01-07 23:53:44 +00:00
15063d79d3
intel/genxml: Update SAMPLER_STATE structure
...
Add new ANISOTROPIC_FAST filter mode value to the Min/MagModeFilter
field.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32738 >
2024-12-31 21:49:41 +00:00
edb33b47ab
intel/genxml/xe2: Add STATE_SYSTEM_MEM_FENCE_ADDRESS instruction
...
Fixes: 86813c60a4lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32680 >
2024-12-18 17:16:05 +00:00
4bd958243d
intel/genxml: Update COMPUTE_WALKER_BODY
...
For PTL, we can have one more additional walk order along with the
"Thread Group Batch Size" field.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32430 >
2024-12-12 19:56:47 -08:00
41eda955af
intel/genxml: Drop morton walk field from Xe2
...
Looks like this one got added accidently for Xe2. Xe2 doesn't support
Morton dispatch walk order.
Thanks to Rohan for bringing up this during review.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32430 >
2024-12-12 19:56:47 -08:00
08530462bd
anv: implement Wa_16011107343/22018402687 for generated draws
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32059 >
2024-11-12 22:48:39 +00:00
8906816f49
anv,hasvk,genxml: Rename genxml files using verx10
...
It could be confusing that a newer platform named with a smaller
number than a half-generation of an older platform like 'gfx20' and
'gfx75' in xml files.
Down the road, it can be a little worse once we pass something like
'gfx40' when there is already a gfx45.xml for the oldest platform.
Unify naming xml files with verx10 numbers to resolve the issue.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31943 >
2024-11-09 00:04:47 +00:00
17096f87c1
intel: Switch to COMPUTE_WALKER_BODY
...
Stuff COMPUTE_WALKER_BODY in COMPUTER_WALKER in both iris and anv.
This also fixes the tracepoint for ray dispatches. Stuffing
COMPUTE_WALKER_BODY allow us to set the
cmd_buffer->state.last_compute_walker.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31822 >
2024-10-29 15:54:43 +00:00
acb1c45a8b
intel/genxml: Start Xe3 support
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31838 >
2024-10-26 07:39:29 +00:00
2483f8f7cd
intel/genxml: Do small fixes in gfx20 definition of STATE_COMPUTE_MODE
...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796 >
2024-10-22 15:24:32 +00:00
86ed5ec78e
intel/genxml: Append 'Z Async Throttle settings' to gfx125 definition of STATE_COMPUTE_MODE
...
DG2 has the 'Force Non-Coherent' fields but MTL and ARL has
'Z Async Throttle settings', so here adding the missing one.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796 >
2024-10-22 15:24:32 +00:00
8cb08830e6
intel/genxml: introduce L3 Fabric Flush for gfx12
...
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764 >
2024-10-08 08:45:40 +00:00
c1af71c9c2
anv,iris: prefix the argument format with XI for a upcoming refactor
...
Backport-to: 24.2
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30690 >
2024-08-20 09:41:51 +00:00
c2bbdda39b
intel/genxml: fix length of HCP_FQM_STATE for gen20 and 125
...
Fixes: 7f280e1e93zzoon@igalia.com >
Reviewed-by: Dave Airlie <airlied@redhat.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: David Heidelberg <david@ixit.cz >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30558 >
2024-08-08 19:43:41 +09:00
8cc492cb26
genxml: unify some bits between Gfx8/Gfx11/Gfx12.5
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30539 >
2024-08-06 17:55:18 +00:00
46e02ee861
intel/genxml: adds a value of reference pic to HCP_SURFACE_STATE
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:59 +00:00
7f280e1e93
intel/genxml: fix some length of HCP_FQM_STATE
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:59 +00:00
663f9eb740
intel/genxml: Adds more VDENC commands
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:59 +00:00
3eb69b9577
intel/genxml: fix the length of VDENC_DS_REF_SURFACE_STATE
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:59 +00:00
e79cad5af0
intel/genxml: Add missing fields for HCP_SLICE_STATE
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:59 +00:00
9425ba6f2b
intel/genxml: update VDENC instructions
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:59 +00:00
b97d440bc5
intel/genxml: change the length of MFX_QM_STATE
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:58 +00:00
5057a33fe3
intel/genxml: add a missing value for MFX_SURFACE_STATE
...
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27810 >
2024-08-02 07:15:58 +00:00
6bc9a57173
intel/genxml: add the BLT and COMP_CTX0 versions of the TR-TT registers
...
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30252 >
2024-07-22 10:04:33 -07:00
68215332a8
build: pass licensing information in SPDX form
...
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Acked-by: Dylan Baker <dylan.c.baker@intel.com >
Acked-by: Eric Engestrom <eric@igalia.com >
Acked-by: Daniel Stone <daniels@collabora.com >
Signed-off-by: David Heidelberg <david@ixit.cz >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29972 >
2024-06-29 12:42:49 -07:00
1c92b31888
intel/genxml,blorp,common: Update 3DSTATE_PS command (xe2)
...
From Bspec 56423 (r58507), the legacy full resovling and
partial resolving options are gone since Xe2. They also
cause hang on Xe2 if not disabled.
Some suggested code from Nanley Chery <nanley.g.chery@intel.com > is
included.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906 >
2024-06-26 05:25:43 +00:00
Sagar Ghuge