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Author SHA1 Message Date
Adam Jackson 514ba16d95 rusticl: Enable out-of-order execution 
Ought to work, let's find out.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12029
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31672>
 2024-10-22 00:03:48 +00:00
Karol Herbst 1798597637 radeonsi: move si_compute::global_buffers to si_context 
si_set_global_binding is a context function, but it touches the bound
compute program. As radeonsi also advertizes PIPE_CAP_SHAREABLE_SHADERS
this function is supposed to be safe when the same compute state object is
bound to multiple contexts at once.

In order to fix this data race global_buffers is moved to si_context so it
becomes context private data instead.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31672>
 2024-10-22 00:03:48 +00:00
Christian Gmeiner fad599a619 etnaviv: Enable ARB_framebuffer_no_attachments 
There is not much needed to pass the supported tests.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31578>
 2024-10-21 23:27:30 +00:00
Amber 9ace01edbe tu, ir3: Implement VK_KHR_shader_atomic_int64 for a7xx. 
Passes dEQP-VK.glsl.atomic_operations.*64bit*

Signed-off-by: Amber Harmonia <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27776>
 2024-10-21 21:47:44 +00:00
Amber a3afe22dc9 nir: add pass to lower atomic arithmetic to a loop with cmpxchg. 
Signed-off-by: Amber Harmonia <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27776>
 2024-10-21 21:47:44 +00:00
Amber 7d0870e5d5 ir3: add support for 64 bit atomics 
Signed-off-by: Amber Harmonia <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27776>
 2024-10-21 21:47:44 +00:00
Amber 5628a01523 ir3: add encoding support for 64-bit atomics introduced in a7xx. 
Signed-off-by: Amber Harmonia <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27776>
 2024-10-21 21:47:44 +00:00
Mary Guillemard 84d57e1fb1 nir: Move atomic_op_to_alu to common code 
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27776>
 2024-10-21 21:47:44 +00:00
quic_lkondred 334af37697 freedreno: Add support for Adreno 663 GPU 
Add support to enable basic functionality of Adreno 663 GPU.

Signed-off-by: quic_lkondred <quic_lkondred@quicinc.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31211>
 2024-10-21 21:05:57 +00:00
Rebecca Mckeever c2299b6642 panvk/csf: Implement vkCmdExecuteCommands 
Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31159>
 2024-10-21 19:39:07 +00:00
Rebecca Mckeever 3513960fe6 panvk: Move rendering info to panvk_rendering_state struct 
Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31159>
 2024-10-21 19:39:07 +00:00
Rebecca Mckeever ddb2f6f1fa panvk: Track VkFormats for depth and stencil attachments 
These can be used directly in vk_meta_rendering_info.

Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31159>
 2024-10-21 19:39:07 +00:00
Rebecca Mckeever 26a03222ef panvk/csf: Split tiler flags initialization into two steps 
The first step conditionally updates the tiler flags based on dirty bits,
and the second step is the override flags, which are unconditionally
updated at draw time.

Use pan_pack_nodefaults() to avoid default initialized fields.

Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31159>
 2024-10-21 19:39:07 +00:00
Rebecca Mckeever 07346ea1e6 panvk/csf: Set and clear vb.dirty flag 
Fixes: 5544d39f44 ("panvk: Add a CSF backend for panvk_queue/cmd_buffer")

Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31159>
 2024-10-21 19:39:07 +00:00
Marek Olšák fb6184f89c nir: add shader_info::tess::tcs_same_invocation_inputs_read(_indirect) 
We need both the same-invocation usage mask and cross-invocation usage
mask. The AMD reason is below.

Cross-invocation TCS input access doesn't prevent the same-invocation
fast path in AMD hw because it's just a different way to load the same
data, and we want to use both paths for the same TCS input based on
the load instruction. The fast path can't be used for indirect access,
which is gathered separately for same-invocation access.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31645>
 2024-10-21 18:53:51 +00:00
Rhys Perry 8221367fba radv: use explicitly sized types for some radv_shader_info members 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31593>
 2024-10-21 15:52:53 +00:00
Rhys Perry 4383a917e6 radv: optimize VS input load components to constants earlier 
This helps some linking optimizations.

fossil-db (navi21):
Totals from 2262 (2.85% of 79395) affected shaders:
MaxWaves: 57680 -> 57738 (+0.10%); split: +0.11%, -0.01%
Instrs: 1061526 -> 1053937 (-0.71%); split: -0.79%, +0.07%
CodeSize: 5766352 -> 5736784 (-0.51%); split: -0.60%, +0.08%
VGPRs: 89376 -> 89000 (-0.42%); split: -0.43%, +0.01%
Latency: 4102938 -> 4059773 (-1.05%); split: -1.14%, +0.08%
InvThroughput: 1105885 -> 1092291 (-1.23%); split: -1.24%, +0.01%
VClause: 18917 -> 18972 (+0.29%); split: -0.12%, +0.41%
SClause: 28839 -> 28115 (-2.51%); split: -3.32%, +0.81%
Copies: 73396 -> 72671 (-0.99%); split: -1.63%, +0.65%
PreSGPRs: 65866 -> 65838 (-0.04%); split: -0.22%, +0.17%
PreVGPRs: 69752 -> 69278 (-0.68%)
VALU: 680351 -> 673489 (-1.01%); split: -1.03%, +0.02%
SALU: 121459 -> 121515 (+0.05%); split: -0.00%, +0.05%
VMEM: 29632 -> 30021 (+1.31%); split: -0.02%, +1.33%
SMEM: 73744 -> 73836 (+0.12%); split: -0.01%, +0.14%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31593>
 2024-10-21 15:52:53 +00:00
Rhys Perry 9784165de5 radv: fix output statistic for fragment shaders 
This is a per-component bit mask (0xf for each output).

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 0e0c2574d1 ("radv: Add shader stats for inputs and outputs.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31593>
 2024-10-21 15:52:52 +00:00
Marek Olšák 45d8cd037a ac/nir: rewrite ac_nir_lower_ps epilog to fix dual src blending with mono PS 
Unigine Heaven with AMD_DEBUG=mono has incorrect rendering on gfx11
because it doesn't set nir_io_semantics::dual_source_blend_index for
the second output, resulting in garbage asm.

Instead of trying to find out what's wrong, I decided to rewrite this
to make it the same as the LLVM IR path. It simplifies the code and fixes
Unigine Heaven with AMD_DEBUG=mono.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31669>
 2024-10-21 12:06:14 +00:00
Eric Engestrom d117411309 {freedreno,intel}/ci: add missing tracking of merge-skips.txt files 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31739>
 2024-10-21 10:22:57 +00:00
Eric Engestrom ee0d782229 {freedreno,intel}/ci: rename "premerge-skips.txt" to "merge-skips.txt" to accurately reflect what they are 
This also means the infrastructure added by @gallo in 1dc64d0613
("ci: Use merge-skips files during merge pipelines") can be used and all
the manual adding of these files can be dropped, reducing the likeliness
of bugs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31739>
 2024-10-21 10:22:57 +00:00
Eric Engestrom bb98949134 ci: rename "freedreno" farm to "google-freedreno" 
There are 3 freedreno farms: google, collabora, and valve.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31709>
 2024-10-21 09:36:05 +00:00
Eric Engestrom 18489da224 freedreno/ci: use {freedreno,turnip}{,-manual}-rules 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31709>
 2024-10-21 09:36:05 +00:00
Eric Engestrom 51125f8b39 freedreno/ci: add {freedreno,turnip}{,-manual}-rules to simplify the rest of the code 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31709>
 2024-10-21 09:36:05 +00:00
Pavel Ondračka 9672f9732f r300/ci: add new RV410 flakes 
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31753>
 2024-10-21 08:22:32 +00:00
Georg Lehmann 10951bb11a aco: fix 64bit extract_i8/extract_i16 
The old code only sign extended to 32bit, with a zero hi half.

Fixes: 1f2518ef9f ("aco: implement nir_op_extract/nir_op_insert")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31734>
 2024-10-21 07:13:57 +00:00
Georg Lehmann 894c4f0c78 meson: remove selinux option 
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31656>
 2024-10-21 01:14:35 +00:00
Mary Guillemard 4bc2d221c9 winsys/nouveau: Reformat to stop relying on tabs 
Also remove .editorconfig as we don't need it anymore.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31667>
 2024-10-19 17:24:46 +02:00
Mary Guillemard f9e72b7fcb winsys/nouveau: Rework to use u_pipe_screen_lookup_or_create 
All the boilerplate can be removed to use u_pipe_screen_lookup_or_create
instead.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31667>
 2024-10-19 17:24:46 +02:00
Caio Oliveira 019770f026 intel/brw: Add SHADER_OPCODE_VOTE_* 
Add opcodes for VOTE_ALL, VOTE_ANY and VOTE_EQUAL.  The first two
are also used for the quad variants.  Move their lowering from
NIR conversion to brw_lower_subgroup_ops.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31029>
 2024-10-19 02:44:20 +00:00
Caio Oliveira f20df2984d intel/brw: Ensure BROADCAST() value respect register alignment 
If we have a non-register-aligned source, MOV it to a new register
so that the invariant expected when generating SHADER_OPCODE_BROADCAST
is respected.

Added to ensure a later patch won't hit the `src.subnr == 0` assertion
in brw_broadcast() generation code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31029>
 2024-10-19 02:44:20 +00:00
Caio Oliveira d97381efd8 intel/brw: Add fs_builder::BROADCAST() helper 
Include in the helper which already take care of using exec_all() and
taking the first component of the result.  Both are expected by
SHADER_OPCODE_BROADCAST.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31029>
 2024-10-19 02:44:20 +00:00
Valentine Burley f3ef27e0b9 ci: Add global ANGLE skips for its waiver 
ANGLE has a waiver for certain XFB tests, but this wasn't properly applied
on Alder Lake and these tests weren't skipped there.

Add a global angle-skips.txt file so that we don't have to keep copy-pasting
these skips.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31721>
 2024-10-18 20:39:33 +00:00
C Stout 2fef9e9029 u_gralloc: include dep_android_mapper4 as needed 
Since it is not included in dep_android.

Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30353>
 2024-10-18 19:21:18 +00:00
Eric Engestrom c4e8e3fb2f zink+nvk/ci: document more flakes seen 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31740>
 2024-10-18 17:57:45 +00:00
Eric Engestrom 3a7881d126 zink+nvk/ci: mark a few tests as fixed 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31740>
 2024-10-18 17:57:45 +00:00
Sergi Blanch Torne a41c4cc1fd WIP: Re-enable Comet Lake 
There is a fresher device type with a CML GPU, with also a bigger number of
boards. Those are more reliable, so also we can remove the manual rules.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26830>
 2024-10-18 16:33:15 +00:00
Mike Blumenkrantz b4e18fb188 vdpau: fail context create if driver does not support video 
not all drivers support this, and forcing them to implement stubs
is not how gallium works

cc: mesa-stable

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31736>
 2024-10-18 15:54:41 +00:00
Mike Blumenkrantz fd0b20e8e8 va: fail context create if driver does not support video 
not all drivers support this, and forcing them to implement stubs
is not how gallium works

cc: mesa-stable

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31736>
 2024-10-18 15:54:41 +00:00
David Heidelberg 49d5dcebd5 ci/freedreno: switch to dash instead of underscore, same as rest of the CI 
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31723>
 2024-10-18 15:21:16 +00:00
Mike Blumenkrantz 45eb3bfd32 device-select: only try wayland/x11 if the required vars are set 
don't try to infer connections, as this may deadlock compositors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31738>
 2024-10-18 14:47:10 +00:00
Christian Gmeiner f4f527cd3e etnaviv: isa: Add img_load instruction 
Blob generates such img_load's for piglit's tests/cl/program/execute/image-read-2d.cl

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31674>
 2024-10-18 13:33:51 +00:00
Christian Gmeiner 1562e51f34 etnaviv: isa: Add clamp0_max instruction 
Reverse engineered with the following OpenCL kernel:

kernel void add(global float* out, float a, float b) {
  float r;

  _viv_asm(CLAMP0MAX, r, a, b);

  out[0] = r;
}

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31674>
 2024-10-18 13:33:50 +00:00
Christian Gmeiner 5fa4c1a191 compiler/rust: Copy NirInstrPrinter from NAK 
Switch NAK to it.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31706>
 2024-10-18 12:43:52 +00:00
Pierre-Eric Pelloux-Prayer 5607c7ee49 ac/surface: fix determination of gfx12_enable_dcc 
For surfaces without a modifier, the surf_size check wasn't
necessary, but it was also invalid since surf_size is set later
(in gfx12_compute_miptree).

Since it's not required anyway, drop this check.

Fixes: 060d5dacfd ("ac: add gfx12 DCC shared code")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31683>
 2024-10-18 14:04:04 +02:00
Pierre-Eric Pelloux-Prayer 19fa5561be radeonsi: fix radeon_canonicalize_bo_flags domain handling 
ffs(VRAM, GTT) returns the GTT bit as it's the smaller.

Simplify the code by explicitely selecting VRAM when both
domains are active, otherwise assert that only 1 bit is set.

Fixes: 593f72aa21 ("winsys/amdgpu-radeon: rework how we describe heaps")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31683>
 2024-10-18 14:04:02 +02:00
Pierre-Eric Pelloux-Prayer bb08596645 radeonsi/gfx12: fill missing dcc tiling info 
Display DCC support has been enabled in 0bb83a4060 but this TODO
was forgotten.
Now that the kernel is fixed, we can set the related fields.

Fixes: 0bb83a4060 ("ac/surface: finish display DCC for gfx12")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31683>
 2024-10-18 14:03:46 +02:00
Daniel Stone a5a5a50ae8 ci/angle: Update ANGLE, reduce build times 
ANGLE currently pulls absolutely loads of stuff that we don't need. Fix
it up so we don't need to do that anymore, so it's much faster to build.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31716>
 2024-10-18 10:40:31 +00:00
Collabora's Gfx CI Team 19ef6b247e Uprev Piglit to 791e420b2628c1e35eea81b3bafdb1c904a141e8 
https://gitlab.freedesktop.org/mesa/piglit/-/compare/7ce69da1199d12ed0ddaa251ed489750523798fb...791e420b2628c1e35eea81b3bafdb1c904a141e8

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31716>
 2024-10-18 10:40:31 +00:00
Pavel Ondračka 33c8dc4f18 nir/nir_group_loads: reduce chance of max_distance check overflow 
Helps for the case when max_distance is set to ~0, where the pass would now
only create groups of two loads together due to overflow. Found while
experimenting with this pass on r300, however the only driver currently
affected is i915.

With i915 this change gains around 20 shaders in my small shader-db
(most notably some GLMark2, Unigine Tropics, Tesseract, Amnesia) at
the expense of increased register pressure in few other cases.
I'm assuming this is a good deal for such old HW, and this seems like what
was intended when the pass was introduced to i915, but anyway this
could be tweaked further driver side with a more optimized max_distance
value. Only shader-db tested.

Relevant i915 shader-db stats (lpt):
total tex_indirect in shared programs: 1529 -> 1493 (-2.35%)
tex_indirect in affected programs: 96 -> 60 (-37.50%)
helped: 29
HURT: 2
total temps in shared programs: 3015 -> 3200 (6.14%)
temps in affected programs: 465 -> 650 (39.78%)
helped: 1
HURT: 91

GAINED: 20

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: GKraats <vd.kraats@hccnet.nl>
Fixes: 33b4eb149e
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31529>
 2024-10-18 09:21:22 +00:00