6e035c01fb
Revert "gallium: make handles of set_global_binding 64 bit"
...
This reverts commit e1ffb72a05
2020-03-10 22:41:26 +00:00
e1ffb72a05
gallium: make handles of set_global_binding 64 bit
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needed by CL
Signed-off-by: Karol Herbst <kherbst@redhat.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072 >
2020-03-10 22:06:19 +00:00
0541350e3a
pan/bi: Implement comparison opcodes via BI_CMP
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Pretty straightforward for the moment. Ideally these would be fused into
csel/branches but that will come a bit later.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:26:00 +00:00
6409896ca7
pan/bi: Print source types unconditionally
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We track them all now, let's use them.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:26:00 +00:00
20c7d57ede
pan/bi: Specify comparison op for BI_CMP
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...and adjust printing so we can use it as an op name.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:26:00 +00:00
08ab7cecd9
pan/bi: Lower b2f to bcsel
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Since we can get a zero for free and a one inlined into the constant,
the obvious turns out to be efficient (while allowing flexibility for
boolean size).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
d3823551b4
pan/bi: Implement nir_op_bcsel
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No condition fusing yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
3a1baafede
pan/bi: Import algebraic pass from midgard
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We'll need some of these at least.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
55f0d811e4
pan/bi: Add isub op
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Can't be a regular ADD since there's no negate modifier for integers
(it's a different opcode entirely).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
acab788578
pan/bi: Disable lower_sub
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For float, fixing up the modifier ourselves is easy. For int, we have a
dedicated isub instruction anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
1216a63ff2
pan/bi: Implement fabs, fneg as fmov with mods
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Fusing will come later with the appropriate NIR support.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
8ed79c9ed7
pan/bi: Handle special ops in NIR->BIR
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Only on supported GPUs at the moment; for older Bifrost that don't
support these, I'm not sure yet where the right place to do the lowering
is. NIR algebraic rules would be "nice" but probably impractical -- but
it wouldn't be hard to do it directly in BIR (as a lowering pass or
alternative implementation).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
b674e39d72
pan/bi: Add BI_SPECIAL_* enum
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To disambiguate the different special ops from each other.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
c862234ab3
pan/bi: Add a bunch of ALU ops
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These are all regular ALU ops found in GLES2 which makes them
particularly nice targets at the moment. Just translate straight to our
IR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
5a5896cd76
pan/bi: Implement fsat as mov.sat
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Soon we'll have a NIR support to handle this the Right Way along with
pos and sat_signed support, but we'll always need the fallback anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
48e50efd5d
pan/bi: Allow inlining constants
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This will allow us to optimize out the constant moves (although that
will require a DCE pass which has yet to be written).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
929baf3f88
pan/bi: Add initial handling of ALU ops
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We do the bare minimum translation, just enough for fmov/fadd/fmul right
now with no modifiers / inlined constants / etc. The rest is to come!
But hopefully I got bitsize handling right this time around.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
330e9a6696
pan/bi: Lower vec* to writemasks in NIR
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I was hoping not to tread down this path but it seems inevitable now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
69c66ffd84
pan/bi: Remove bi_load
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This is now made redundant with writemasks, so let's regularize the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
e9d480ca1b
pan/bi: Introduce writemasks
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I feel so dirty. But this will let the IR be a lot more flexible seeing
as we really are vector in a certain sense (I/O, small types)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
795646d8f8
pan/bi: Generalize swizzles to avoid extracts
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We'd really rather not emit extracts. We are approaching on a vector IR
anyway which is annoying but really necessary to handle I/O and fp16
correctly. So let's just go all the way and deal with swizzles and masks
within reason; it'll still be somewhat saner in the long-term.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
9b8cb9f5ae
panfrost: Move mir_to_bytemask to common code
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...also so we can start sharing code properly between the panfrost
compilers.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139 >
2020-03-10 19:25:59 +00:00
ba03e308b6
freedreno/fdperf: set locale
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Set local to get numbers printed w/ commas.. much easier to read that
way.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119 >
2020-03-10 16:52:02 +00:00
30dd059925
freedreno/computerator: add performance counter support
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Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119 >
2020-03-10 16:52:02 +00:00
af68b0d346
vulkan/wsi: Return an error if dup() fails
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Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135 >
2020-03-10 16:39:27 +00:00
34d2637fa7
vulkan/wsi: Don't leak the FD when GetImageDrmFormatModifierProperties fails
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Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135 >
2020-03-10 16:39:27 +00:00
3c96e25de7
freedreno/ir3: try to avoid syncs
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Update postsched to be better aware of where costly (ss) syncs would
result. Sometimes it is better to allow a nop or two, to avoid a
sync quickly after an SFU.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
cc82521de4
freedreno/ir3: round-robin RA
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In the second (scalar pass) use the information about # of registers
used in the first pass as the target max, and round-robin within that
range. This generally gives the post-RA sched pass more opportunities
to re-order instructions to remove nop's.
Also, we can be a bit clever when assigning dest registers for SFU
instructions, by picking the register used for it's src (if available
and already assigned). This avoids some (ss) syncs caused by write
after read hazards. (Ie. the SFU instruction will read it's own src
before writing dest.)
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
b2b349096f
freedreno/ir3: track register usage in first RA pass
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We'll use the feedback from the first pass to select a target register
usage in the second pass.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
9ae93be8fb
freedreno/ir3: fix has_latency_to_hide
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Also count tex-prefetch instructions. And only let the no-latency rule
kick in for frag shaders.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
b6eb11295a
freedreno/ir3: split out has_latency_to_hide()
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Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
dd2e050a84
util/ra: move NO_REG to header
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In the select_reg callback, I want to be able to determine if a given
node is already assigned, and if so what physical register has been
assigned.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
36aed70b59
util/ra: spiff out select_reg_callback
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Add a parameter so the callback can know which node it is selecting a
register for. And remove the graph parameter, as it is unused by
existing users, and somewhat unnecessary (ie. the callback data could
be used instead).
And add a comment so $future_me remembers how this works.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
b3efa2a4da
freedreno: fix FD_MESA_DEBUG=inorder
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Fixes: 2c07e03b79robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
752b9985be
freedreno/ir3: add simplified stall estimation
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Doesn't take into account stalls that result from a register written in
a different block, etc. But this should be more useful than just using
number of (ss)'s by trying to estimate how costly a given sync is.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
64ae2ef8bb
freedreno/ir3: remove extra nops inserted in scheduler
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They were inserting a nop between back to back SFU instrucions. But
that doesn't actually appear to be required. And they get stripped out
later anyways before legalize.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
ad2ff7a278
freedreno/computerator: add hrsq/hlog2/hexp2
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Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
4a8e4c18d2
freedreno/ir3: also lower lowp frag outputs
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Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
3535797e8c
nir/print: show variable precision
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Signed-off-by: Rob Clark <robdclark@chromium.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071 >
2020-03-10 16:01:39 +00:00
10eee6d8c6
intel/tools: Fix compilation with UBSan
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Compilation failed with several similar errors:
../src/intel/tools/aub_read.c:322:4: error: case label does not reduce to an integer constant
322 | case MAKE_HEADER(TYPE_AUB, OPCODE_AUB, SUBOPCODE_HEADER):
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132 >
2020-03-10 15:20:26 +00:00
74be835a84
i965: Use gl_vertex_format in brw_vertex_element.
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State upload needs to cope with the vertex format
rather than with the full attribute data.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
e62b82a693
i965: Make use of the vertex format functions in i965.
...
v2: Style fixes.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
cf929823bf
mesa: Provide gl_vertex_format accessors.
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Provide the same set of VAO and current value gl_vertex_format
accessor functions like we have for the gl_array_attributes.
For most purpose the vertex format is what we need.
v2: Style fixes.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
1641c872ed
mesa: Remove now unused _mesa_draw_attrib.
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Reviewed-by: Matt Turner <mattst88@gmail.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
305724dd7b
mesa: Remove now unused _mesa_draw_attrib_and_binding.
...
Reviewed-by: Matt Turner <mattst88@gmail.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
4ccda7bfd9
i965: Remove glbinding from brw_vertex_element.
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v2: Rebase.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
38db4f1720
i965: Reorder workaround flags computation.
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Vertex processing workaround flags can be split into
array and current vertex attributes. By that we
can use specific access functions for these different
vertex attribute kinds. This finally obsoletes
some access functions that I introduced last winter
for a smooth transition.
v2: Style fixes.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
e53fd073be
i965: Split merge_inputs and clear_buffers.
...
The merge_inputs function handles that part that changes when the
inputs change. The clear_buffers function triggers when we may need
a new upload. Thus the merge_inputs can be limited to be once
per brw_draw_prims.
v2: Move declaration of attribute index into the for scope.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
de579ffba2
i965: Test original vertex array pointer to skip array upload.
...
Rather than do a NULL pointer check on a pointer that may be offset by the
min-max index range of an GL draw operation, execute the NULL test on the
original vertex array pointer.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
b684030c3a
i965: Use the VAOs binding information in array setup.
...
The change basically reimplements array setup by walking
the gl_contex::Array._DrawVAO on a per binding sequence.
In this way we can make direct use of the application
provided minimum set of buffer objects and emit fewer relocs.
v2: Rebase onto:
compiler: Move double_inputs to gl_program::DualSlotInputs
v3: Rebase onto introduction of gl_vertex_format
v4: Reorder and extend patch series.
v5: Split out two hunks into seperate patches.
v6: Avoid using GL* types.
Reviewed-by: Matt Turner <mattst88@gmail.com >
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308 >
2020-03-10 14:28:37 +00:00
Karol Herbst