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Author SHA1 Message Date
Marek Olšák babd87f2e0 radeonsi: make cs_preamble_state optional 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák 976edae839 radeonsi: sort registers in si_init_cs_preamble_state according to GPU gen 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák 88fe9dea7a radeonsi: sort registers in si_emit_initial_compute_regs according to GPU gen 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák 1c6eca23fd radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING 
Copied from PAL. Higher values break tessellation, which I was only able
to reproduce with register shadowing enabled.

Fixes: 0bf3e6fae7 "radeonsi/gfx10: double the number of tessellation offchip buffers per SE"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák d244a25c07 radeonsi: add missing initialization of registers 
(random initial gfx10 commit:)
Fixes: 78cdf9a99f - amd/addrlib: add gfx10 support

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Mike Blumenkrantz 3f783a3c50 zink: omit Lod image operand in ntv when not using an image texture dim 
according to spec, this is invalid (and it's not being used anyway)

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>
 2020-07-22 14:01:29 +00:00
Mike Blumenkrantz 0ef5e19874 zink: add some asserts for building access chains in ntv 
we're never going to pass a 0 here, and it's going to be an error if we do

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>
 2020-07-22 14:01:29 +00:00
Mike Blumenkrantz 2af22051c0 zink: handle texelFetchOffset with offsets 
we need to explicitly add the offset in this case since it's not available
as a spirv param

fixes spec@glsl-1.30@execution@fs-texelfetchoffset-2d

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>
 2020-07-22 14:01:29 +00:00
Mike Blumenkrantz 6587f41e11 zink: use helper function to handle uvec/bvec types 
bit_size of 1 means we use a bool type here, 32 means uint, so we can just
handle that automatically for all relevant cases

ref shaders@glsl-vs-continue-in-switch-in-do-while

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5911>
 2020-07-22 14:01:29 +00:00
Rhys Kidd 7dc4fe6fb4 nvc0: add documentation for nve4+ (Kepler) COPY class 
Has been utilised within nouveau in place of the former M2MF class, which was
dropped for Kepler in PGRAPH in favour of:

  - a new P2MF object that only does simple upload; and
  - PCOPY took over responsibility of M2MF's other DMA functions.

Autogenerated headers from envytools commit 32659e654170cb03038ccf2cb165decd3a2409d6

NVIDIA documentation released at:
  https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/dma-copy/cla0b5.h

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5982>
 2020-07-22 05:49:08 +00:00
Rhys Kidd 203d565b19 nvc0: fix macro define for NVE4_COPY() 
Fixes: e44089b2f7 ("nvc0: add initial support for nve4+ (Kepler) chipsets")
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5982>
 2020-07-22 05:49:08 +00:00
Connor Abbott bb5b136b45 freedreno: Use common guardband helper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5950>
 2020-07-21 14:26:18 +00:00
Alyssa Rosenzweig 86a6597714 panfrost: Remove unused batch_fence->ctx 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5995>
 2020-07-21 13:57:43 +00:00
Alyssa Rosenzweig f18e5371cf panfrost: Remove unused batch_fence->signaled 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5995>
 2020-07-21 13:57:43 +00:00
Alyssa Rosenzweig 64d6f56ad2 panfrost: Allocate syncobjs in panfrost_flush 
For implementing panfrost_flush, it suffices to wait on only a single
syncobj, not an entire array of them. This lets us wait on it directly,
without coercing to/from syncfds in the middle (although some complexity
may be added later to support Android winsys).

Further, we should let the fence own the syncobj, tying together the
lifetimes and thus removing the connection between syncobjs and
batch_fence.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5995>
 2020-07-21 13:57:43 +00:00
Alyssa Rosenzweig 85a2216fe4 panfrost: Skip specifying in_syncs 
With the current kernel UABI, there is no benefit to explicitly
specifiying dependencies, since the kernel by design adds implicit
dependencies to any referenced BOs. This is something we'd like to
address in the future, but efficient handling with future kernels will
require a tweaked design in userspace as well. So let's do the obvious
thing now, and extend later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5995>
 2020-07-21 13:57:43 +00:00
Alyssa Rosenzweig e5ef5a381e panfrost: Remove wait parameter to flush_all_batches 
It is always false now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5995>
 2020-07-21 13:57:43 +00:00
Alyssa Rosenzweig 0c4db886b6 panfrost: Avoid wait=true flushing all batches 
What is intended is to flush the batches and wait on a particular BO at
a later time. Explicitly forcing a wait immediately is redundant.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5995>
 2020-07-21 13:57:43 +00:00
Karol Herbst 3a7cd7bd65 nv50/ir: initialize persampleInvocation to false 
Fixes: random KHR-GL45.sample_variables.mask.* fails
Fixes: 66ed9792ed ("nv50: Clear nv50_ir_prog_info of dead and codegen specific variables")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6001>
 2020-07-21 12:16:54 +00:00
Karol Herbst 618b355504 nv50/ir/tgsi: silence warning about unhandled GS_INPUT_PRIM property 
Fixes: 66ed9792ed ("nv50: Clear nv50_ir_prog_info of dead and codegen specific variables")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6001>
 2020-07-21 12:16:54 +00:00
Kenneth Graunke 576c53dadf iris: Fix CCS check in iris_texture_subdata(). 
The intention here was to check "Would the GPU be able to compress
this if we used the PBO-based texture upload path?"  Prior to Gen12,
that meant checking for CCS_E.  On Gen12, there are a lot more types
of compression, and basic CCS_E was replaced by GEN12_CCS_E, making
this check simply not work, so we'd take the CPU path instead.

Instead, check if it has CCS, and isn't the basic "fast clear" CCS_D.

Fixes: 39f06e2848 ("iris: Implement pipe->texture_subdata directly")
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6005>
 2020-07-21 09:10:37 +00:00
Bas Nieuwenhuizen 7b7917a424 radeonsi: Inhibit clock-gating for perf counters. 
Otherwise most counters return 0. Should be much more user friendly
than having to totally disable clock-gating on the kernel cmdline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5972>
 2020-07-20 23:56:26 +00:00
Icecream95 3ec252a3b2 panfrost: 8x MRT support 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5892>
 2020-07-20 14:15:49 +00:00
Icecream95 978f963ea4 panfrost: Use more tilebuffer sizes 
This will be needed for 8x MRT with 128-bit framebuffer formats.

Adds support for 256-bit, 1024-bit, and 2048-bit tilebuffer allocations,
depending on the amount of data required.

v2: Squash commits (Alyssa)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5892>
 2020-07-20 14:15:49 +00:00
Icecream95 c1d3d39e97 panfrost: Fake RGTC support 
For most GPUs RGTC is disabled, so it needs to be emulated, using the
fake_rgtc option of u_transfer_helper.

Passes the rgtc-teximage tests in piglit.

v2: Update docs/features.txt (Alyssa)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5975>
 2020-07-20 09:54:49 -04:00
Pierre-Eric Pelloux-Prayer d2a3ca289f radeonsi: adjust epitch for PIPE_FORMAT_R8G8_R8B8_UNORM 
This fix si_compute_copy_image for yuyv image (so using PIPE_FORMAT_R8G8_R8B8_UNORM).

With this change, the following gst pipeline produce the expected results for various
image sizes (with or without AMD_DEBUG=nodma):

gst-launch-1.0 filesrc location=input.jpg ! jpegparse ! vaapijpegdec ! filesink location=output.yuv

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5841>
 2020-07-20 10:32:44 +00:00
Gert Wollny 1fa36c1d3d d600/sfn: write stream outputs to correct mem ring 
Fixes: arb_gpu_shader5-xfb-streams
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny 21d296a481 r600/sfn: Make the pin_to_channel generic 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny 3ea847e6d1 r600/sfn: Only use sample mask if the according shader key is set 
This fixes all the piglits from arb_sample_shading "samplemask * *"
with the nir backend.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny c91979c634 r600: Add shader key item to identify when the sample mask should be used 
The sample mask must be applied when more then one sample is available or
multisamplig is not enabled, so add a shader key to track this.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny 05df4bfbca r600/sfn: Fix default z swizzle for GDS instructions 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny 2779aa360e r600/sfn: Fix Ring output swizzle masks 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny c18b1c6df5 r600/sfn: Add a forced output swizzle for depth write 
This makes sure no components are written that shouldn't be written.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny d31ef0b7a4 r600/sfn: correct handling of loading vec4 with fetching constants 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny aca99e6fc9 r600/sfn: Add option to get a temp value for a specific channel 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny 258618815b r600/sfn: emit texture instructions in one block 
Setting the offset must happen in the same CF like using it, so don't
emit ALU instruction between the tex instructions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny deccf02246 r600/sfn: Pipe through requesting a register at a given channel 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Gert Wollny 55cc712991 r600/sfn: lower rotate ALU ops 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5963>
 2020-07-20 09:32:51 +00:00
Dave Airlie 41c7bb6ec0 llvmpipe: add framebuffer fetching support (v1.1) 
v1.1:
Merge two if blocks (Roland)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5914>
 2020-07-20 15:14:09 +10:00
Dave Airlie 0e0b6d477b llvmpipe/cs: respect render condition 
Running complete CTS turned up a missing cond render.

Fixes KHR-GL45.compute_shader.conditional-dispatching

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5944>
 2020-07-19 15:07:26 +10:00
Rob Clark 79b0651c24 freedreno: whitespace fix 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5957>
 2020-07-18 09:11:35 -07:00
Rob Clark 835201dd76 freedreno: small comment re-word 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5957>
 2020-07-18 09:11:35 -07:00
Mike Blumenkrantz 2b343238a1 zink: free all ntv allocations after creating shader module 
these are all fairly large sources of leaks

Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5887>
 2020-07-18 07:51:37 +00:00
Mike Blumenkrantz adc4f3896a zink: free pipeline cache during program destroy 
more leaks

Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5887>
 2020-07-18 07:51:37 +00:00
Mike Blumenkrantz 1ff2d195b0 zink: destroy descriptor pools on context destroy 
this is a big leak

Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5887>
 2020-07-18 07:51:37 +00:00
Mike Blumenkrantz 7116decfce zink: destroy gfx program when a shader is freed 
there's no sense in having these objects sitting around when they can
never be used again

requires adding a zink_context* pointer to each program in order to prune
the hash table entry

Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5887>
 2020-07-18 07:51:37 +00:00
Icecream95 0ef168d513 panfrost: Fix calls to panfrost_flush_batches_accessing_bo 
The function now takes a bool flush_readers instead of an access type,
but some calls were not updated.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5962>
 2020-07-18 01:36:59 +00:00
Icecream95 858cc13eb2 panfrost: Make panfrost_bo_wait take a wait_readers bool 
panfrost_bo_wait is often used after
panfrost_flush_batches_accessing_bo, so make them take similar
arguments for consistency.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5962>
 2020-07-18 01:36:59 +00:00
Alyssa Rosenzweig 610af7e1ac panfrost: Enable FP16 by default 
I see no reason to hide this. The small hit in cycle count is offset in
practice by the increase in thread count. So let's ship it and get some
testing.

If this regresses a workload:

1. Open an issue on the tracker and attach an apitrace.
2. In the meantime set PAN_MESA_DEBUG=nofp16 to override.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5960>
 2020-07-17 23:37:13 +00:00
Eric Anholt 4080f8bf2b freedreno/a2xx: Fix compiler warning in disasm. 
warning: converting a packed ‘instr_cf_t’ {aka ‘union <anonymous>’}
pointer (alignment 1) to a ‘uint16_t’ {aka ‘short unsigned int’} pointer
(alignment 2) may result in an unaligned pointer value
[-Waddress-of-packed-member]

We may know that we'll only ever have aligned instr_cf_ts, but gcc
doesn't.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5955>
 2020-07-17 21:47:32 +00:00