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Author SHA1 Message Date
Jesse Natalie
4b69ae8e1e nir_opt_deref: ptr_as_array(deref_cast<T*>(x))[0] isn't the same as x[0] if the cast has alignment 
This breaks CLOn12's handling of CL CTS test_basic vector_creation for char3 (at least).
Removing this cast causes us to try to load from a deref with no alignment info.

Fixes: 99bb2a4d ("nir/opt_deref: Don't remove casts with alignment information")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
 2021-04-13 03:40:23 +00:00
Jesse Natalie
70aefe3449 vtn: Support scoped control barriers for OpenCL too 
The current handling for SPIR-V memory semantics is very specific to
the wording in the SPIR-V spec, which breaks its handling of OpenCL
(compared to what we had working downstream before merging upstream).

Update/relax the logic here to support CL's barrier(CLK_GLOBAL_MEM_FENCE);

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
 2021-04-13 03:40:23 +00:00
Marek Olšák
f9b527a9a5 radeonsi: unify internal compute with SSBOs in si_launch_grid_internal_ssbos 
just deduplicate the code

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
ec60526035 radeonsi: move binding the internal compute shader into si_launch_grid_internal 
instead of doing it in each function

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
aa8a6e5f26 radeonsi: enable DCC for MSAA 4x and 8x on gfx9 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
3120113ee7 radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9 
MSAA 4x and 8x should only clear the first 2 samples because other samples
are uncompressed. The compute shader only clears that subset of DCC.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
8b95f51ef1 radeonsi: fix and enable full DCC with MSAA 2x on gfx9 
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
7e68fae25f ac,radeonsi: rewrite DCC retiling without the DCC retile map 
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.

The RADV code is disabled.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
35adf91de7 ac/surface: limit the number of swizzle modes that can have displayable DCC 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
5ce8c440dd ac/surface: add a test of DccAddrFromCoord prototype outside of addrlib 
The test takes over 2 minutes on a 12C/24T CPU with OpenMP.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
cd2832ee51 meson: add an optional OpenMP dependency for AMD tests 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
df2cbdd2e3 amd/addrlib: expose DCC address equations to drivers 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
8771d45a74 ac/surface/tests: fix a random segfault in the modifier test 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
23b2cf032a ac/surface/tests: test Sienna Cichlid and Navy Flounder 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
1b3dbde3b9 ac/surface: only apply the 3D swizzle mode tuning to gfx10+ 
This fixes an addrlib failure on gfx9.

Fixes: b43f40166c "ac/surface: select best swizzle mode for 3D sampler performance"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
ec42f52013 radeonsi: allow DCC_DECOMPRESS via CB with MSAA textures 
The shader-based codepath doesn't support it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
8277732358 radeonsi: try to fix DCC coherency issues with DCC decompression 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
f7c58559f5 radeonsi: refine fast clears for small buffers, always use them for large HTILE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
06b6af596c radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW 
This adds a clear_buffer compute shader that does read-modify-write to
update a subset of bits in HTILE.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
84fa21a611 radeonsi: when transitioning to TC-compat HTILE, try to do a proper clear 
instead of always clearing to uncompressed.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
558ab3310d radeonsi: enable DCC fast clears for non-zero mipmap levels and 0/1 clear values 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
9defe8aca9 radeonsi: implement fast Z/S clears using clear_buffer on HTILE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
e2714d5dd4 radeonsi: indent the code for TC-compatibility HTILE transition 
So that HTILE clears can be nicely inserted into a new else statement there.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
fcd01ad444 radeonsi: add si_can_fast_clear_depth/stencil helpers 
for later use

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
4dd8d58ad5 radeonsi: clean up some mess around htile_stencil_disabled 
Set the final value in si_texture_create_object, so that other places
don't have to derive it redundantly.

The only thing to remember is that HTILE stencil can be enabled when
stencil is not present, and it can be disabled when stencil is present
due to various workarounds.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
bcd1a69f79 radeonsi: parallelize Z/S conversion into TC-compatible with fast color clears 
It's not really a fast clear, but it's the next logical step towards doing
HTILE clears here.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
fb72d41b18 radeonsi: implement Z/S fast clear for non-zero mipmap levels 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
6434b0b652 radeonsi: implement per-level DCC and CMASK fast clears for gfx10+ 
Fast clears are only used for level 0. This enables clearing level 0
of CMASK and DCC on gfx10+ when there are multiple mipmap levels.
vi_dcc_clear_level can also clear any level now.

Mipmapped array textures are still cleared slowly.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
059f042fb1 radeonsi: allow trivial DCC clears for shared textures with DCC constant encode 
This relaxes the existing restriction.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
c00b314ae4 radeonsi: restructure DCC disablement into a switch 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Marek Olšák
fa43d61953 radeonsi: don't cache FMASK transactions from CB in L2 
FMASK is usually pretty large. It's better to leave the cache to shaders.
FMASK stores are still cached, but they can be evicted sooner, which is
the same as other color stores. Only DCC, HTILE, and CMASK are cached.

I haven't benchmarked this, but it seems like the right thing to do.
This only affected APUs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
 2021-04-13 03:17:42 +00:00
Nanley Chery
bc1f715076 iris: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC 
With a resolution of 1600x1200, I measured FPS increases in:

* glxgears 18.04% +/- 0.65% (n=691)
* Nexuiz    3.58% +/- 0.09% (n=553)

compared to the master branch at commit
3f614c6f7c.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery
4785aad6a0 iris: Support RC_CCS_CC modifier in plane queries 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery
f02951d727 iris: Support clear color plane imports for RC_CCS_CC 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery
11a0584c48 isl: Describe I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC 
v2. Simplify the diff. (Jason)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery
7a69942d29 drm-uapi: Update drm_fourcc.h for new TGL modifier 
Pull in the header from drm-next commit
32c3d9b0f51ee1e6bb0160496b97e50b5caca4d0. Among other things, this
brings in the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Nanley Chery
0092219cfe iris: Set BO maps to NULL in bo_free 
bo_free is called on external BOs when there are no objects left which
reference them. The function unmaps the address range associated with
any maps which occured. However, if the BO is busy (not idle), it
doesn't mark the pointer to the start address as invalid. This can lead
to a segfault later on.

At the end of bo_free, these BOs are still present in the handle hash
table. If such a BO is reused (i.e., when a DMABUF with the same handle
is reimported) and the driver attempts to get another mapping, the
bufmgr will incorrectly assume that the map pointer is still valid and
reuse it. This leads to a segfault. Set the pointer to NULL to mark it
as invalid.

Enables iris to run and pass the piglit test,
ext_image_dma_buf_import-reimport-bug.

Cc: mesa-stable
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
 2021-04-13 02:53:11 +00:00
Mike Blumenkrantz
5a61a4dbfa aux/trace: do deep dumps of fb state for triggered traces 
having the full surface info available here is very useful

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
 2021-04-13 02:04:22 +00:00
Mike Blumenkrantz
5ac3bb806b aux/trace: dump current fb state on trigger-mode draw if it hasn't been seen yet 
this info is important to have for a given frame, but it requires that the base
structs be copied and stored to the trace context for later use

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
 2021-04-13 02:04:22 +00:00
Mike Blumenkrantz
5ecffaa7a6 aux/trace: enhance trigger mode to dump context states during bind 
when dumping a single frame, the creation info for these states hasn't been
dumped yet, so always dump it during bind so it's visible

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
 2021-04-13 02:04:22 +00:00
Chia-I Wu
51216d656d venus: check vn_renderer_info::vk_xml_version 
When crosvm does not support venus, it still advertises
VIRGL_RENDERER_CAPSET_VENUS but provides no or zeroed capset data.
vk_xml_version will be zero.

It is a good idea to verify vk_xml_version anyway.

v2: print required version suggested by Ryan

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10192>
 2021-04-13 01:03:52 +00:00
Eric Anholt
f86e0a519d ci: bump bare-metal kernel to bring in an a530 stability fix 
and while I'm here, drop a workaround for back when we had binary
snapshots of the a530 kernel without compression support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10047>
 2021-04-13 00:40:56 +00:00
James Park
f3bd5f9590 amd: Hide drm_fourcc.h on Windows 
Declare missing definitions instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9708>
 2021-04-13 00:24:02 +00:00
James Park
7dfc9e4431 amd: Hide amdgpu_drm.h on Windows 
Declare missing definitions instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9708>
 2021-04-13 00:24:02 +00:00
Icecream95
821d68652d panfrost: Add fast path for graphics work group computation 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
 2021-04-12 23:53:41 +00:00
Icecream95
c8620005d2 panfrost: Align BO size to 4096 bytes 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
 2021-04-12 23:53:41 +00:00
Icecream95
1b41707bbc panfrost: Only add resource checksum BOs to the batch once 
Previously panfrost_batch_add_bo was called MAX_MIP_LEVELS times on
the same batch.

Fixes: cbf68b21fb ("panfrost: Move checksum_bo to panfrost_resource")

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
 2021-04-12 23:53:41 +00:00
James Park
1aeebac4e6 ac/rgp: BSD elf library compatibility 
Allow compilation on Windows using modified BSD elf library.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9210>
 2021-04-12 22:50:52 +00:00
Thong Thai
e62c7e7c6c radeon: Add cropping to encoded H.265 when padding is used 
Because the VCN encoder needs the surface to be memory aligned, the
resolution of the image passed to the encoder might be larger and have
extra padding added - this change crops the resulting output to
compensate for the extra padding that might have been added.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4559
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10137>
 2021-04-12 22:42:53 +00:00
Vasily Khoruzhick
77fdabdfa5 lima: limit number of draws per job 
Otherwise we may hit tile heap size limit if an app issues too many
draws per job.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10121>
 2021-04-12 22:34:12 +00:00