When importing libdrm_radeon code [1][2] it was somehow missed
that what libdrm has in one r600_pci_ids.h, Mesa has split
into r600_pci_ids.h and radeonsi_pci_ids.h. So, devices
with ids from radeonsi_pci_ids.h were not considered valid for
radeon_surface_manager_new.
This commit changes that, thus fixing radeonsi for these
devices.
[1] commit 1299f5c50a
[2] commit 3aa7497cc0
Fixes: 1299f5c50a
Signed-off-by: Ivan A. Melnikov <iv@altlinux.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33940>
It is expected that inputs and prefetches are always in the first block.
However, ir3_create_empty_preamble would create blocks before the first
one, leaving inputs after the preamble. This causes issues with
(probably among others) spilling/RA where precolored inputs could
illegally reuse the spill base register.
Fixes RA validation failures on a7xx for
dEQP-VK.ray_query.multiple_ray_queries.vertex_shader
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: f3026b3d3e ("ir3: add some preamble helpers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33977>
For empty BVHs we shouldn't emit any leaf nodes, but there is one
invocation to encode the root node. Guard leaf node encoding so that
invocation doesn't try writing any leaves.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33985>
Prime blit can be used in setups like venus on lavapipe over vtest. It's
native env so Venus relies on renderer side driver to tell about the pci
info, while lavapipe doesn't implement that extension, which ends up
with mismatched gpu thus prime blit.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33956>
The swizzle check was too strict, we actually don't care about the
swizzle on the constant source at this point, it is only checked
later whether the constant source actually has the correct form.
So this effectively enables INV and BIAS presub on R300/R400.
RV370 stats:
total instructions in shared programs: 85379 -> 84948 (-0.50%)
instructions in affected programs: 15669 -> 15238 (-2.75%)
helped: 336
HURT: 81
total presub in shared programs: 1318 -> 2991 (126.93%)
presub in affected programs: 797 -> 2470 (209.91%)
helped: 0
HURT: 514
total omod in shared programs: 387 -> 384 (-0.78%)
omod in affected programs: 9 -> 6 (-33.33%)
helped: 3
HURT: 0
total temps in shared programs: 13290 -> 13243 (-0.35%)
temps in affected programs: 1388 -> 1341 (-3.39%)
helped: 91
HURT: 52
total consts in shared programs: 81922 -> 81855 (-0.08%)
consts in affected programs: 173 -> 106 (-38.73%)
helped: 67
HURT: 0
total cycles in shared programs: 126746 -> 126560 (-0.15%)
cycles in affected programs: 30752 -> 30566 (-0.60%)
helped: 255
HURT: 124
LOST: shaders/godot3.4/22-69.shader_test FS
GAINED: shaders/ck2/172.shader_test FS
GAINED: shaders/tesseract/389.shader_test FS
GAINED: shaders/tesseract/393.shader_test FS
GAINED: shaders/unity/64-DeferredPointShadows.shader_test FS
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33915>
Previously asynchronous descriptor set allocation is only enabled when
the VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT bit is not set.
However, some engine would use that bit but alloc/free with identical
descriptor set layout. So this change extends the async set alloc to
cover that since the spec has guaranteed no fragmentation there.
Besides, a pool before any descriptor set free is also considered w/o
fragmentation. so this change extends to cover here as well. Both
would also help with dEQP run time since all descriptor pools involved
are with that bit set.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33966>
We get a kernel message "You are adding an unorder point to timeline!"
on many CTS runs. This stems from us SIGNALing the queue syncobj then
WAITing but not reseting it. It is assumed by the time we get to
panvk_queue_submit_init_signals() that the value is 0, however it is 1
due to the previous calls.
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Fixes: 5544d39f ("panvk: Add a CSF backend for panvk_queue/cmd_buffer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33943>
VEGA10, RENOIR, NAVI10, RAPHAEL and NAVI31 are covered, they passed
100% of 25 runs each.
NAVI21 and VANGOGH still don't enable video testing in CI because I
got few hangs during my last stress test. Need to be stress tested
again.
Note that the kernel in Mesa CI is too old and doesn't have latest
firmwares that should fix the remaining failures.
GFX6-8 have different issues like GPU hangs on Polaris10, so it's not
yet enabled in CI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33968>
At least, NAVI10, NAVI21 and NAVI24 are affected by this what looks
like a hardware bug when primitive restart is changed and no context
registers are written between draws. It seems the hardware doesn't
consider primitive restart at all in this situation.
Adding SQ_NON_EVENT(0) as suggested by Marek seems to fix it reliably
without introducing any overhead. It's basically a NOP packet that adds
a small delay.
Fixes new VKCTS coverage dEQP-VK.transform_feedback.primitive_restart.*.
Also fixes this old vkd3d-proton issue.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7258
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33929>
