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7563 Commits

Author SHA1 Message Date
Boris Brezillon 56251f924d nir: Add a nir_sysvals_to_varyings() helper 
Allow backends to turn some sysvals into input varyings so the frontend
(in our case spirv_to_nir()) doesn't have to bother selecting which
one is expected.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13017>
 2021-10-07 19:45:35 +00:00
Jason Ekstrand b71bdc3404 nir/algebraic: Add some opts for comparisons of comparisons 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13167>
 2021-10-07 18:21:11 +00:00
Jason Ekstrand 7abf3955ca nir/algebraic: Add some boolean optimizations 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13167>
 2021-10-07 18:21:11 +00:00
Jason Ekstrand c8b2be0b95 nir/algebraic: Lower fisfinite 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13167>
 2021-10-07 18:21:11 +00:00
Rhys Perry f3723822a4 nir/lower_tex: add lower_to_fragment_fetch_amd 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12214>
 2021-10-07 15:36:39 +00:00
Rhys Perry 225fe37c14 nir: add _amd suffix to fragment_mask_fetch and fragment_fetch texops 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12214>
 2021-10-07 15:36:39 +00:00
Marcin Ślusarz 3a18963b08 nir/print: pad 64-bit constants with zeroes 
... just like other-size constants are.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13223>
 2021-10-07 10:49:15 +00:00
Emma Anholt 7dde279db5 nir-to-tgsi: Avoid emitting TXL just for lod 0 on non-vertex shaders. 
Prompted by comparing virgl fails and finding that it has issues with
immediate args to TXL/TXB, at least.

Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12800>
 2021-10-06 03:44:17 +00:00
Ian Romanick cb28361642 nir/algebraic: Small optimizations for SpvOpFOrdNotEqual and SpvOpFUnordEqual 
No shader-db changes on any Intel platform.

Fossil-db results:

All Intel platforms had similar results. (Ice Lake shown)
Instructions in all programs: 144380118 -> 143692823 (-0.5%)
SENDs in all programs: 6920822 -> 6920822 (+0.0%)
Loops in all programs: 38299 -> 38299 (+0.0%)
Cycles in all programs: 8434782176 -> 8423078994 (-0.1%)
Spills in all programs: 206830 -> 204469 (-1.1%)
Fills in all programs: 318737 -> 313660 (-1.6%)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12320>
 2021-10-06 01:53:47 +00:00
Ian Romanick 0cf25f559f spirv: Generate shorter code for SpvOpFUnord comparisons 
No shader-db or fossil-db changes on any Intel platform.

v2: Keep the flt <-> fge switcharoo local to the SpvOpFUnordLessThan,
etc. handling.  Add a comment explaining why the suboptimal
SpvOpFUnordEqual implementation is used here.  Suggested by Caio.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12320>
 2021-10-06 01:53:47 +00:00
Ian Romanick 1ce48ce91d spirv: SpvOpFUnordNotEqual doesn't need special treatment 
The NIR fneu opcode already matches the "unordered not equal" semantics
of the SPIR-V opcode.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12320>
 2021-10-06 01:53:47 +00:00
Ian Romanick f8148b861f spirv: Minor cleanup in SpvOpFOrdNotEqual 
v2: Add a comment explaining why the suboptimal SpvOpFOrdNotEqual
implementation is still used here.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12320>
 2021-10-06 01:53:47 +00:00
Ian Romanick 803b754b81 spirv: Silence unused parameter warnings in vtn_alu.c 
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12320>
 2021-10-06 01:53:47 +00:00
Alyssa Rosenzweig 3e8f540753 nir: Add Mali-specific derivative opcodes 
Add derivative opcodes fddx_must_abs_mali/fddy_must_abs_mali satisfying:

   fabs(fdd*_must_abs_mali(v)) = fabs(fdd*(v))

The sign of their result is undefined.

On Bifrost and Valhall, these unsigned derivatives can be implemented
more efficiently than the correctly-signed counterparts, since the sign
fixup requires extra ALU instructions. On backends where this is the
case, it is useful to optimize fabs(fdd*(v)) to
fabs(fdd*_must_abs_mali(v)). This pattern comes up with the GLSL builtin
`fwidth`.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12332>
 2021-10-06 00:40:57 +00:00
Lionel Landwerlin d0a3a11258 nir/lower_io: preserve all metadata when no progress 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13168>
 2021-10-05 11:23:23 +00:00
Marcin Ślusarz e26328582a nir: preserve all metadata when nir_opt_vectorize doesn't make progress 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13189>
 2021-10-05 10:02:54 +00:00
Marcin Ślusarz 54df09c8d4 nir: preserve all metadata when nir_propagate_invariant doesn't make progress 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13189>
 2021-10-05 10:02:54 +00:00
Marcin Ślusarz 804c56f1a2 nir: preserve all metadata when nir_lower_int_to_float doesn't make progress 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13189>
 2021-10-05 10:02:54 +00:00
Marcin Ślusarz 87ecdd4eff glsl: preserve all metadata when lower_buffer_interface_derefs doesn't make progress 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13189>
 2021-10-05 10:02:54 +00:00
Jesse Natalie 82c69c9a9d compiler/clc: Preserve OCL kernel arg type metadata on LLVM13 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13177>
 2021-10-04 18:16:01 +00:00
Jesse Natalie 3a752256f5 compiler/clc: Null extensions should mean all supported, not all 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13177>
 2021-10-04 18:16:01 +00:00
Lionel Landwerlin 445996379b clc: let user specify the targetted SPIRV version 
This version is given to the LLVM-SPIRV translator. On the SPIRV-Tools
side of things, we want to use the highest available version to be
sure to be able to parse back what was generated.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13113>
 2021-10-03 19:32:54 +00:00
Lionel Landwerlin 72fd81d0ac clc: print warnings/errors on their own line 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13113>
 2021-10-03 19:32:54 +00:00
Lionel Landwerlin 3c8c817ae7 clc: add allowed extension for compile parameter 
The LLVM-SPIRV translator can include a bunch of capabilities into the
generated SPIRV which is not what you always want. That include
internal Intel specific capabilities from the translator.

v2: Rename options
    Fixup checks (Jesse)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13113>
 2021-10-03 19:32:54 +00:00
Boris Brezillon 7cd402c9c8 nir/lower_blend: Shrink blended result if needed 
Make sure the new and old sources have the same number of components,
otherwise the NIR validation pass complains.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
 2021-09-30 16:54:42 +02:00
Boris Brezillon 3e07b8d4f8 nir/lower_blend: Make sure we're not passed scaled formats 
SCALED formats are interpreted as floats, but not in the usual [0, 1]
or [-1, 1] range, meaning that the blend lowering logic can't directly
apply to those. Assert that the format being passed is not a scaled
format.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
 2021-09-30 16:54:42 +02:00
Boris Brezillon 15b4cab4d5 nir/lower_blend: Don't lower RTs whose format is set to NONE 
The caller doesn't necessarily want to lower blend operations on all
render targets since some of them might be supported natively (panvk
will be in that case). Let's just skip RTs that have a format set to
PIPE_FORMAT_NONE to allow that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
 2021-09-30 16:54:42 +02:00
Boris Brezillon 637cd5ac00 nir/lower_blend: Pad src to a 4-component vector 
nir_ssa_for_src() is not supposed to pad the src vector if
dst->num_components > src->num_components. Let's pad things explicitly
with nir_pad_vector().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
 2021-09-30 16:54:42 +02:00
Boris Brezillon 641bed3103 nir: Make sure src->num_components < dst->num_components in nir_ssa_for_src() 
The NIR validation complains if the swizzle accesses a component that's
not present in the source.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13060>
 2021-09-30 16:54:42 +02:00
Vadym Shovkoplias 36c241be01 driconf, glsl: Add a vs_position_always_precise option 
This is basically the same workaround as in 9b577f2a88 (driconf, glsl: Add a
vs_position_always_invariant option) commit but for tesselation evaluation
shaders. Some applications do not mark outputs as precise in tesselation
evaluation shaders which can lead to different results in case some
optimizations were applied.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Fixes: 09705747d7 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13027>
 2021-09-30 10:46:39 +00:00
Jason Ekstrand d2264489ce compiler/clc: grab opencl-c.h from the system path by default 
By default we use the header installed opencl-c.h header. But in the
case Mesa is compiled for microsoft clon12 we keep the injected file.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
 2021-09-30 07:09:08 +00:00
Jason Ekstrand 8490766f53 compiler/clc: Clean ups 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
 2021-09-30 07:09:08 +00:00
Jason Ekstrand 1506ea2ecb Move a bunch of the CLC stuff from src/microsoft to common code 
The D3D12-specific stuff isn't useful to have in common code but all the
stuff to invoke clang really should be common.

v2: Rebase (Lionel)

v3: Define a new clc_libclc_new_dxil() entrypoint to create a clc
    context with DXIL nir_options (Jesse)

v4: Fixup meson build (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9156>
 2021-09-30 07:09:08 +00:00
Rob Clark 2b826582d8 isaspec: De-duplicate bitset encoding 
bitset encoding tends to have a lot of duplication, for ex. many
instructions with the same encoding modulo the fixed pattern.  Now that
encode_bitset is split out into it's own template, so that we can
capture the result, use a hash table to de-duplicate the bitset encoding
into "snippet" functions so that bitset cases with identical encoding
can re-use the same generated code.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
 2021-09-29 22:59:43 +00:00
Rob Clark 8726ed7221 isaspec: Split encode_bitset() into it's own template 
In the next patch, we are going to want to be able to capture the result
of rendering the template as a py variable, which I don't think you can
do otherwise with a <%def>.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
 2021-09-29 22:59:43 +00:00
Rob Clark 72db4e51f3 isaspec: Fix comment 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
 2021-09-29 22:59:43 +00:00
Rob Clark cd3ee83ca5 isaspec: Remove unused leftovers 
These were never used, leftovers from an earlier iteration of isaspec
which used an RPN based thing for expressions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13049>
 2021-09-29 22:59:43 +00:00
Lionel Landwerlin 52c0e6e5b3 spirv: switch Groups capability to non AMD specific field 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13081>
 2021-09-29 15:40:20 +00:00
Lionel Landwerlin daa8a81d99 nir: fix opt_memcpy src/dst mixup 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f6667cb0ce ("nir: Add a memcpy optimization pass")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13079>
 2021-09-28 16:36:08 +00:00
Lionel Landwerlin f349c8ab4b spirv: don't bother initializing variables to Undef 
If an OpVariable's initializer is undef, there is no need to
initialize the variable.

v2: Comment the code (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13030>
 2021-09-27 19:04:42 +00:00
Lionel Landwerlin a17d24d901 spirv: workaround LLVM-SPIRV Undef variable initializers 
The LLVM-SPIRV translator creates variables with initializers, but
most of those are actually undef initializers. We can just skip
composites that are entirely made of undefs, but for partially undefs,
we will still zero initialize.

v2: Rename wa_llvm_spirv_undef_initializer to wa_llvm_spirv_ignore_workgroup_initializer (Caio)
    Limit workaround to OpenCL (Caio)
    Make workaround clearer (Caio)

v3: Only apply workaround on workgroup storage (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13030>
 2021-09-27 19:04:42 +00:00
Lionel Landwerlin a17928639d spirv: avoid shadowing local variable 
v2: rename s/eval/elem_val/ (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13030>
 2021-09-27 19:04:42 +00:00
Lionel Landwerlin 9d9e67d118 spirv: don't fail on CapabilitySubgroupDispatch if supported 
Since only Anv uses the value, I'm only enabling this on anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 518693c3ec ("spirv: Handle the SubgroupSize execution mode")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13034>
 2021-09-24 20:23:14 +00:00
Rhys Perry e43007af56 nir/opt_if: add opt_if_rewrite_uniform_uses 
Turns:
if (a == (b=readfirstlane(a)))
   use(a)
into:
if (a == (b=readfirstlane(a)))
   use(b)

Improves divergence analysis and lets us scalarize use(a). Improves
Cyberpunk 2077 performance.

fossil-db (Sienna Cichlid, Cyberpunk 2077):
Totals from 57 (10.56% of 540) affected shaders:
VGPRs: 4904 -> 4040 (-17.62%)
CodeSize: 624360 -> 626828 (+0.40%); split: -0.06%, +0.46%
MaxWaves: 656 -> 824 (+25.61%)
Instrs: 119770 -> 119447 (-0.27%); split: -0.49%, +0.22%
Latency: 1950256 -> 1633110 (-16.26%); split: -16.26%, +0.00%
InvThroughput: 364852 -> 292089 (-19.94%)
VClause: 1512 -> 1008 (-33.33%)
SClause: 2693 -> 3196 (+18.68%)
Copies: 10050 -> 9955 (-0.95%); split: -3.34%, +2.40%
Branches: 3476 -> 3547 (+2.04%)
PreSGPRs: 4003 -> 5076 (+26.80%)
PreVGPRs: 4709 -> 3810 (-19.09%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12472>
 2021-09-24 18:41:18 +00:00
Rhys Perry 69f9a96af1 nir: add nir_src_components_read() 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12472>
 2021-09-24 18:41:18 +00:00
Caio Marcelo de Oliveira Filho 240e60ba76 nir/lower_io_to_vector: Allow Task/Mesh to load from outputs 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12951>
 2021-09-24 14:35:15 +00:00
Caio Marcelo de Oliveira Filho 895cfca641 spirv: Identify non-temporal memory access 
Map it to the existing ACCESS_STREAM_CACHE_POLICY access mode.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12945>
 2021-09-21 21:55:54 +00:00
Christian Gmeiner ca0f892191 compiler/isaspec: add alignment support 
This helps to get a really nice and aligend disasm output.
Just use :align=X to define where in the line the field
should be printed.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Christian Gmeiner eae96d0c4c compiler/isaspec: keep track of written data 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00
Christian Gmeiner f0104a6c72 compiler/isaspec: add print(..) helper 
To support field alignment we need to keep track of how much
data we have printed to our out FILE. This is a prep commit.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11321>
 2021-09-21 20:25:31 +00:00