nir-to-tgsi: Avoid emitting TXL just for lod 0 on non-vertex shaders.

Prompted by comparing virgl fails and finding that it has issues with
immediate args to TXL/TXB, at least.

Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12800>

src/compiler/nir/nir.c

@@ -2236,6 +2236,17 @@ nir_shader_lower_instructions(nir_shader *shader,
    return progress;
 }
 
+/**
+ * Returns true if the shader supports quad-based implicit derivatives on
+ * texture sampling.
+ */
+bool nir_shader_supports_implicit_lod(nir_shader *shader)
+{
+   return (shader->info.stage == MESA_SHADER_FRAGMENT ||
+           (shader->info.stage == MESA_SHADER_COMPUTE &&
+            shader->info.cs.derivative_group != DERIVATIVE_GROUP_NONE));
+}
+
 nir_intrinsic_op
 nir_intrinsic_from_system_value(gl_system_value val)
 {

src/compiler/nir/nir.h

@@ -5443,9 +5443,12 @@ bool nir_shader_uses_view_index(nir_shader *shader);
 bool nir_can_lower_multiview(nir_shader *shader);
 bool nir_lower_multiview(nir_shader *shader, uint32_t view_mask);
 
+
 bool nir_lower_fp16_casts(nir_shader *shader);
 bool nir_normalize_cubemap_coords(nir_shader *shader);
 
+bool nir_shader_supports_implicit_lod(nir_shader *shader);
+
 void nir_live_ssa_defs_impl(nir_function_impl *impl);
 
 const BITSET_WORD *nir_get_live_ssa_defs(nir_cursor cursor, void *mem_ctx);

src/compiler/nir/nir_lower_tex.c

@@ -1373,13 +1373,8 @@ nir_lower_tex_block(nir_block *block, nir_builder *b,
        * derivatives.  Lower those opcodes which use implicit derivatives to
        * use an explicit LOD of 0.
        */
-      bool shader_supports_implicit_lod =
-         b->shader->info.stage == MESA_SHADER_FRAGMENT ||
-         (b->shader->info.stage == MESA_SHADER_COMPUTE &&
-          b->shader->info.cs.derivative_group != DERIVATIVE_GROUP_NONE);
-
       if (nir_tex_instr_has_implicit_derivative(tex) &&
-          !shader_supports_implicit_lod) {
+          !nir_shader_supports_implicit_lod(b->shader)) {
          lower_zero_lod(b, tex);
          progress = true;
       }

src/gallium/auxiliary/nir/nir_to_tgsi.c

@@ -2776,6 +2776,20 @@ nir_to_tgsi_lower_tex_instr(nir_builder *b, nir_instr *instr, void *data)
    if (nir_tex_instr_src_index(tex, nir_tex_src_coord) < 0)
       return false;
 
+   /* NIR after lower_tex will have LOD set to 0 for tex ops that wanted
+    * implicit lod in shader stages that don't have quad-based derivatives.
+    * TGSI doesn't want that, it requires that the backend do implict LOD 0 for
+    * those stages.
+    */
+   if (!nir_shader_supports_implicit_lod(b->shader) && tex->op == nir_texop_txl) {
+      int lod_index = nir_tex_instr_src_index(tex, nir_tex_src_lod);
+      nir_src *lod_src = &tex->src[lod_index].src;
+      if (nir_src_is_const(*lod_src) && nir_src_as_uint(*lod_src) == 0) {
+         nir_tex_instr_remove_src(tex, lod_index);
+         tex->op = nir_texop_tex;
+      }
+   }
+
    b->cursor = nir_before_instr(instr);
 
    struct ntt_lower_tex_state s = {0};