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Author SHA1 Message Date
Michel Dänzer
4292fb2139 wsi/x11: Use PresentOptionAsync for MAILBOX present mode with Xwayland 
This allows Xwayland to forward buffers to the Wayland compositor ASAP
for fullscreen / undecorated windows, which in turn allows true mailbox
behaviour in the Wayland compositor.

Without this, Xwayland has to emulate the mailbox behaviour itself,
which it cannot do as well as the Wayland compositor by design.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>
 2021-01-07 15:00:07 +01:00
Michel Dänzer
b5268d532a wsi/x11: Detect Xwayland 
The following commits will introduce different behaviour for Xwayland.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>
 2021-01-07 14:58:24 +01:00
Michel Dänzer
1de2fd0cf2 wsi/x11: Always link against xcb-xrandr 
The next commit will make use of it even without
VK_USE_PLATFORM_XLIB_XRANDR_EXT.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>
 2021-01-07 14:57:45 +01:00
Michel Dänzer
1cce8e1101 wsi/x11: Set recognizable name for WSI swapchain queue thread 
This makes it easier to recognize the thread e.g. in a debugger.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8197>
 2021-01-07 14:56:41 +01:00
Pierre-Eric Pelloux-Prayer
07c1504d1b radeonsi: implement SQTT support 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:10:17 +01:00
Pierre-Eric Pelloux-Prayer
a46e830444 radeonsi: add radeon_set_uconfig_reg_seq_perfctr 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:10:17 +01:00
Pierre-Eric Pelloux-Prayer
df5233b977 ac/sqtt: move radv_get_expected_buffer_size to ac 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:10:16 +01:00
Pierre-Eric Pelloux-Prayer
ea6176e63e ac/sqtt: move ac_is_thread_trace_complete to ac 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:10:14 +01:00
Pierre-Eric Pelloux-Prayer
ffdfe136e6 ac/sqtt: move rgp/sqtt def to ac 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:09:57 +01:00
Pierre-Eric Pelloux-Prayer
4ec5cf5318 ac/radv: move radv_rgp.c to ac 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:09:49 +01:00
Pierre-Eric Pelloux-Prayer
bbc245ab2e ac/radv: move sqtt structs and helpers to amd/common 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:09:47 +01:00
Pierre-Eric Pelloux-Prayer
04f6ba113c ac/sqtt: add ac_thread_trace_data 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:09:45 +01:00
Pierre-Eric Pelloux-Prayer
b94104c0c0 radeonsi: pass radeon_cmdbuf to si_cp_dma_wait_for_idle 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:09:25 +01:00
Pierre-Eric Pelloux-Prayer
aa9fe1e423 radeonsi: pass radeon_cmdbuf to emit_cache_flush 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8002>
 2021-01-07 10:09:25 +01:00
Alistair Popple
7f9a084e7e gv100/ir: Use system wide atomics 
Increase the scope of atomic operations from GPU to system. This is
required for support of SVM to ensure atomic access is maintained for
memory buffers that are not local to the current GPU.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7955>
 2021-01-07 08:59:10 +00:00
Alistair Popple
b02e3053ea gv100/ir: Make emitATOM consistent with emitRED 
GV100 code generation uses ATOM instructions for compare-and-swap and
RED instructions for other atomic operations. Make the scope consistent
for both types of operations.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7955>
 2021-01-07 08:59:10 +00:00
Marek Olšák
62703b79a5 radeonsi: remove si_gs_prolog_bits::gfx9_prev_is_vs 
It didn't do anything useful. GS doesn't use the other user SGPRs.
If we decrease the number of user SGPRs we declare for the GS prolog,
we can remove gfx9_prev_is_vs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8344>
 2021-01-06 23:28:04 -05:00
Marek Olšák
b6b6d1ff3c radeonsi: fix hang caused by for loop with exec=0 in LS and ES 
LLVM expects that exec != 0 when entering loops and generates this code
that becomes an infinite loop if exec == 0:

BB5_1:
    vcc_lo = (inverted terminating condition)
    s_and_b32 vcc_lo, exec_lo, vcc_lo
    s_cbranch_vccnz BB5_3    // jump if vcc != 0 (break statement)
    // ... loop body ...
    s_branch BB5_1
BB5_3:

For non-monolithic VS before TCS, VS before GS, and TES before GS,
we set exec = (thread enabledmask), which sets 0 for HS-only and GS-only
waves, causing the infinite loop condition above.

Fix it as follows:
- set exec = ~0 at the beginning
- wrap the whole shader (LS and ES) in a conditional block, so that HS-only
  and GS-only waves jump over it and never enter such a loop

The TES before GS hang can be reproduced by gfxbench:
    testfw_app --gfx egl -w 1920 -h 1080 --gl_api gles -t gl_tess

Fixes: 68d6d097f1 - radeonsi/gfx9: add GFX9 and VEGA10 enums

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8344>
 2021-01-06 23:28:01 -05:00
Dylan Baker
9f9bc35dc0 bin/gen_calendar_entries: Add support for making a release 
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
 2021-01-07 00:07:56 +00:00
Dylan Baker
a450b4550d bin/gen_calendar_entries: Add support for extending a release 
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
 2021-01-07 00:07:56 +00:00
Dylan Baker
bc9e09360f bin: Add script for manipulating the release calendar 
Currently it only handles creating entries for a new rc.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
 2021-01-07 00:07:56 +00:00
Dylan Baker
8587e57f12 docs: store the release-calendar information in csv (and fix tests) 
Restructured text (and markdown) is painful to programatically
manipulate, most python parsers are geared towards writing markdown and
generating html. I'd like to move the calendar updates to being
scripted, as such using csv to store them will be convenient. This also
allows us to simplify our scripting that manipulates the table
considerably.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8341>
 2021-01-07 00:07:56 +00:00
Eric Anholt
e1b7c42cc6 freedreno: Add missing dep on u_tracepoints. 
Fixes: a02dcb970f ("freedreno: Add GPU tracepoints")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8355>
 2021-01-06 23:55:30 +00:00
Eric Anholt
3efbc47c83 freedreno: Mark a615/a618 as also lacking Z24_UINT_S8_UINT support. 
Rob says it's also the case on 618, and presumably 615 as well then, so
make it take the same path as a630.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
 2021-01-06 22:54:14 +00:00
Eric Anholt
1633c9735a freedreno: Disable UBWC on z24s8 on a630. 
Stencil texture sampling (such as what we have to do for BlitFramebuffer)
is broken with UBWC enabled.  We can't just take the
fd_resource_uncompress() path, because that's a blit just like
BlitFramebuffer.

Fixes failure in dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8,
but also the uncaught rendering fails of 4_samples.stencil_index8 and
depth24_stencil8.

Prior to "911ce374caf0 freedreno/a6xx: Fix MSAA clear" we would usually
pass and sometimes flake fail on this test occasionally, thus it being
listed as a flake (though the rendering was actually broken).  Since that
commit, though, we consistently fail on a pixel of the broken rendering,
and thus this was brought to my attention by the #freedreno-ci channel
spam.

Rob took a look at the performance impact of this, and the worst was maybe
up to .5% fps hit on trex.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
 2021-01-06 22:54:14 +00:00
Eric Anholt
6a8601fb24 freedreno/a6xx: Fix z24s8 non-ubwc blits on a630. 
Taken from the logic in turnip (though they have the format table have
8888_unorm and override to z24s8_as_rgba for blits in the ubwc case)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
 2021-01-06 22:54:14 +00:00
Eric Anholt
d6e307dcc5 freedreno/a6xx: Move the IBO pipe2tex down to where it's used. 
For the texture path, the pipe2tex happens in fd6_tex_const_0().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
 2021-01-06 22:54:14 +00:00
Eric Anholt
1c4613f5d4 turnip: Move the limited_z24s8 flag to the shared device info. 
I want to do the same logic in freedreno, so use the same flag.  On
suggestion by robclark, rename it to what it specifically means.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8319>
 2021-01-06 22:54:14 +00:00
Neil Armstrong
11f32b6a05 kmsro: sync Android.mk GALLIUM_TARGET_DRIVERS 
Sync Android.mk GALLIUM_TARGET_DRIVERS names from kmsro meson.build,
notably adding the missing mediatek, meson and rockchip display drivers
names.

It also fixes the imx name into imx-drm as referenced in meson.build
and src/gallium/targets/dri/target.c

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7443>
 2021-01-06 22:34:45 +00:00
Eric Engestrom
e9f3b7aaa4 docs: use a single cell for the branch number 
Fixes: 94c6511757 ("docs: add release schedule for 20.3")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7950>
 2021-01-06 22:28:39 +01:00
Rhys Perry
f7a5b8ed35 vtn: support SpvCapabilitySparseResidency 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Rhys Perry
7d1d4acbd5 nir/lower_tex: fix lower_tg4_offsets with sparse fetches 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Rhys Perry
2d2decc905 nir: add sparse_residency_code_and 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Rhys Perry
4cbdf9ec4d nir,spirv: implement SpvOpImageSparseTexelsResident 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Rhys Perry
1fd8b46667 nir,spirv: add sparse image loads 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Rhys Perry
3a7972f72a nir,spirv: add sparse texture fetches 
Like SPIR-V and GL_ARB_sparse_texture2, these return a residency code. It
is placed in the destination after the rest of the result. If it's zero,
then the texel is resident. Otherwise, it's not resident.

Besides the larger destination and the residency code, sparse fetches
work the same as normal fetches.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Rhys Perry
95819663b7 nir: allow 5 component vectors 
These will be useful for sparse texture instructions and image load
intrinsics.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Rhys Perry
ba4a73a502 nir/tests: fix callback for load/store vectorizer tests 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
 2021-01-06 20:36:38 +00:00
Daniel Schürmann
22b89d9a52 nir/opt_vectorize: fix call to filter function 
Due to the typo, it could happen that instructions
got further vectorized than intended.

Fixes: 8eaf9c61d1 ('nir/opt_vectorize: don't hash filtered instructions')
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8352>
 2021-01-06 19:03:07 +00:00
Vinson Lee
03999595e7 freedreno/afuc: Replace readfile with os_read_file. 
Tested afuc-disasm produced same output.

$ ./builddir/src/freedreno/afuc/afuc-disasm -g 6 src/freedreno/.gitlab-ci/reference/afuc_test.fw > /tmp/afuc_test.asm
$ diff ./src/freedreno/.gitlab-ci/reference/afuc_test.asm /tmp/afuc_test.asm
$ echo $?
0

Suggested-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8290>
 2021-01-06 18:12:34 +00:00
Dylan Baker
18a0f07957 bin/remove get-pick-list.sh files 
These haven't been used for a long time, they've been supersceeded by
pick-ui

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7863>
 2021-01-06 09:56:56 -08:00
Dylan Baker
9ed7adc018 pick-ui: don't handle the mouse 
It's annoying, since it prevents linux "midle click" copy-n-paste

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7863>
 2021-01-06 09:56:52 -08:00
Erik Faye-Lund
96ceca33c1 gallium/util: do not perform n^2 stencil blits 
We already loop n times here, no point in doing n instances as well.

Fixes: e8a40715a8 ("gallium/util: add blitter-support for stencil-fallback")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8301>
 2021-01-06 17:09:16 +00:00
Rob Clark
32a6a13052 freedreno/ir3/parser: Fix pre-a6xx stib parsing 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:53 +00:00
Rob Clark
859c92d7ee freedreno/ir3/parser: a6xx ldib/stib parsing 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:53 +00:00
Rob Clark
b7ea6ec178 freedreno/ir3: Fix pre-a6xx ldgb/stib parsing 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:53 +00:00
Rob Clark
050a449dbb freedreno/ir3: Explicitly flag disasm test vectors that don't parse 
Mark the test cases which aren't supported by ir3_parser.y explicitly,
so we notice future regressions.  And likewise, fail when we see an
unexpected pass, so we don't forget to update the test vectors in the
future as ir3_parser improves.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:53 +00:00
Rob Clark
b073dae5f0 freedreno/ir3: Fix ldg decoding/parsing 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:53 +00:00
Rob Clark
a7e88787f6 freedreno/ir3/parser: Fixup stg parsing and add more tests 
The offset can also be a register, in which case we need to shuffle
around the src order.  Add a few more test vectors to cover each
permutation (no offset, immed offset, gpr offset).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
d6fa130dda freedreno/ir3/parser: Add stgb support 
Note that this conflicts with `stc` on a6xx+, so a good test that the
(new) disasm can handle both cases properly.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00