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Author SHA1 Message Date
Erik Faye-Lund
428fadd71f pvr: remove unused macros 
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38352>
 2025-11-11 10:13:11 +01:00
Tapani Pälli
2741ddd75a anv: fix issues found with indirect data stride 
Use tristate for the aligned setting, otherwise it is always
first disabled which contributes to the condition if we set the
new stride active.

v2: set ByteStride in dword units and take secondary cmdbuf
    in to account (Lionel)

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38349>
 2025-11-11 05:05:43 +00:00
Alyssa Rosenzweig
997b3ebbdb poly: fix cull distance 
More fallout from strict NIR validation but easy to fix. I hit this when
attempting to CTS changes for parent_instr.

Closes: #14245
Fixes: 2f6b4803ab ("nir/validate: expand IO intrinsic validation with nir_io_semantics")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38356>
 2025-11-11 01:34:24 +00:00
Christian Gmeiner
9c31b9b342 etnaviv: blt: Add Z16_UNORM format translation 
Passes dEQP-GLES3.functional.fbo.msaa.4_samples.depth_component16

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38362>
 2025-11-11 00:30:21 +01:00
Christian Gmeiner
0ca826692a etnaviv: blt: Add S8_UINT_Z24_UNORM format translation 
Passes dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_color

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38361>
 2025-11-10 23:59:18 +01:00
Timothy Arceri
595a2fdbd2 glsl: assign block indices in the order they appear 
The hash lookup should be negligible. This makes things
predictable rather than having hash table modifications causing
the order to change, and fixes things for some seemingly buggy games.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13802
Fixes: be5a15f11d ("util/hash_table: start with 16 entries to reduce reallocations")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38300>
 2025-11-10 21:52:25 +00:00
Iván Briano
aa97c23484 brw: shut -Wmaybe-uninitialized up 
Release builds are noisy about flush_type and scope being used
uninitialized, even though they are always set.
Initialize them to the final else values to make GCC happy.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38357>
 2025-11-10 21:06:50 +00:00
Aitor Camacho
f458825d95 kk: Force vertex attribute rebinding when pipeline changes 
Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38325>
 2025-11-10 20:50:54 +00:00
Sagar Ghuge
16f66ffe55 intel/common: Consider 0 threads while setting TG 
In ray tracing dispatch, we have dispatch.threads set to 0 since we
calculate the local_size_x/y/z based on the launch sizes.

This change takes 0 threads into an account and returh the TG size 8 in
such scenarios. Before this change, we were setting TG size to 2.

Fixes: 0c4e1c9efc ("intel/common: Add helper for compute thread group dispatch size")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38229>
 2025-11-10 12:09:30 -08:00
Samuel Pitoiset
6929333b0f ac/surface: ban 256KB swizzle modes for non-MSAA images on GFX11+ 
This seems to hurt more than it helps and AMD drivers also disable
256 KB for non-MSAA.

While we are at it, remove an useless check about GFX12 APUs because
they don't exist.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14237
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38219>
 2025-11-10 19:29:22 +00:00
Georg Lehmann
9ef0c96f26 nir/opt_algebraic: optimize open coded pack_32_2x16 
Foz-DB Navi48:
Totals from 4 (0.00% of 80287) affected shaders:
Instrs: 6231 -> 6101 (-2.09%)
CodeSize: 35916 -> 35156 (-2.12%)
Latency: 72190 -> 71317 (-1.21%)
InvThroughput: 20817 -> 19962 (-4.11%)
VALU: 3145 -> 3029 (-3.69%)
VOPD: 310 -> 312 (+0.65%)

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37937>
 2025-11-10 19:04:32 +00:00
Ian Romanick
d9bed33c11 nir/opt_if: Both parts of logic-joined conditions can be evaluated 
For cases like 'if (X && Y)', both X and Y must be true in the then
branch. Their values are unknown in the else branch. Similarly, 'if (X
|| Y)' must have both X and Y false in the else branch.

The shader-db results are pretty bad, especially on Skylake. Ouch. The
fossil-db results are good enough that they make up for it.

v2: s/alu/alu_src/ in nir_src_parent_instr(use_src) !=
&alu_src->instr. Noticed by Rhys.

shader-db:

Lunar Lake
total instructions in shared programs: 17203905 -> 17196251 (-0.04%)
instructions in affected programs: 668828 -> 661174 (-1.14%)
helped: 352 / HURT: 2

total cycles in shared programs: 879896264 -> 888462774 (0.97%)
cycles in affected programs: 330523984 -> 339090494 (2.59%)
helped: 187 / HURT: 167

total spills in shared programs: 3318 -> 3329 (0.33%)
spills in affected programs: 4 -> 15 (275.00%)
helped: 0 / HURT: 4

total fills in shared programs: 1903 -> 1917 (0.74%)
fills in affected programs: 7 -> 21 (200.00%)
helped: 0 / HURT: 4

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
total instructions in shared programs: 19969129 -> 19961439 (-0.04%)
instructions in affected programs: 665860 -> 658170 (-1.15%)
helped: 354 / HURT: 0

total cycles in shared programs: 884509249 -> 887353784 (0.32%)
cycles in affected programs: 323242817 -> 326087352 (0.88%)
helped: 208 / HURT: 146

total spills in shared programs: 4801 -> 4808 (0.15%)
spills in affected programs: 14 -> 21 (50.00%)
helped: 0 / HURT: 6

total fills in shared programs: 4454 -> 4467 (0.29%)
fills in affected programs: 17 -> 30 (76.47%)
helped: 0 / HURT: 6

Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 19913774 -> 19906147 (-0.04%)
instructions in affected programs: 667348 -> 659721 (-1.14%)
helped: 351 / HURT: 3

total cycles in shared programs: 861253468 -> 864535803 (0.38%)
cycles in affected programs: 325577148 -> 328859483 (1.01%)
helped: 180 / HURT: 174

total spills in shared programs: 3440 -> 3455 (0.44%)
spills in affected programs: 18 -> 33 (83.33%)
helped: 0 / HURT: 8

total fills in shared programs: 1946 -> 1961 (0.77%)
fills in affected programs: 18 -> 33 (83.33%)
helped: 0 / HURT: 8

Skylake
total instructions in shared programs: 19031768 -> 19023604 (-0.04%)
instructions in affected programs: 671633 -> 663469 (-1.22%)
helped: 347 / HURT: 7

total cycles in shared programs: 868474831 -> 868132073 (-0.04%)
cycles in affected programs: 320499758 -> 320157000 (-0.11%)
helped: 246 / HURT: 108

total spills in shared programs: 4024 -> 4063 (0.97%)
spills in affected programs: 28 -> 67 (139.29%)
helped: 0 / HURT: 18

total fills in shared programs: 3722 -> 3746 (0.64%)
fills in affected programs: 34 -> 58 (70.59%)
helped: 0 / HURT: 18

fossil-db:

Lunar Lake
Totals:
Instrs: 928574038 -> 928568364 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 40916656 -> 40916672 (+0.00%)
Send messages: 41467974 -> 41467909 (-0.00%); split: -0.00%, +0.00%
Loop count: 970202 -> 970191 (-0.00%)
Cycle count: 106297789925 -> 106301305901 (+0.00%); split: -0.00%, +0.01%
Spill count: 3424464 -> 3424452 (-0.00%); split: -0.00%, +0.00%
Fill count: 6525458 -> 6525119 (-0.01%); split: -0.01%, +0.00%
Max live registers: 193525368 -> 193524886 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 232027347 -> 232026610 (-0.00%); split: -0.00%, +0.00%

Totals from 1130 (0.06% of 2018793) affected shaders:
Instrs: 2662692 -> 2657018 (-0.21%); split: -0.27%, +0.06%
Subgroup size: 16 -> 32 (+100.00%)
Send messages: 112689 -> 112624 (-0.06%); split: -0.07%, +0.01%
Loop count: 5723 -> 5712 (-0.19%)
Cycle count: 1176696438 -> 1180212414 (+0.30%); split: -0.33%, +0.63%
Spill count: 9895 -> 9883 (-0.12%); split: -0.13%, +0.01%
Fill count: 26892 -> 26553 (-1.26%); split: -1.26%, +0.00%
Max live registers: 215462 -> 214980 (-0.22%); split: -0.30%, +0.08%
Non SSA regs after NIR: 398940 -> 398203 (-0.18%); split: -0.21%, +0.03%

Meteor Lake, DG2, Tiger Lake, Ice Lake, and Skylake had similar results. (Meteor Lake shown)
Totals:
Instrs: 1000318839 -> 1000314218 (-0.00%); split: -0.00%, +0.00%
Send messages: 45548952 -> 45548887 (-0.00%); split: -0.00%, +0.00%
Loop count: 1026441 -> 1026430 (-0.00%)
Cycle count: 92411461807 -> 92395024225 (-0.02%); split: -0.02%, +0.00%
Spill count: 3665265 -> 3665221 (-0.00%); split: -0.00%, +0.00%
Fill count: 6504830 -> 6504801 (-0.00%); split: -0.00%, +0.00%
Max live registers: 121790079 -> 121789811 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 38062488 -> 38062648 (+0.00%)
Non SSA regs after NIR: 256900770 -> 256900038 (-0.00%); split: -0.00%, +0.00%

Totals from 1124 (0.05% of 2284852) affected shaders:
Instrs: 2724110 -> 2719489 (-0.17%); split: -0.24%, +0.07%
Send messages: 112096 -> 112031 (-0.06%); split: -0.07%, +0.01%
Loop count: 5697 -> 5686 (-0.19%)
Cycle count: 960659254 -> 944221672 (-1.71%); split: -1.91%, +0.20%
Spill count: 13791 -> 13747 (-0.32%); split: -0.40%, +0.08%
Fill count: 43216 -> 43187 (-0.07%); split: -0.14%, +0.08%
Max live registers: 114877 -> 114609 (-0.23%); split: -0.31%, +0.07%
Max dispatch width: 12768 -> 12928 (+1.25%)
Non SSA regs after NIR: 412320 -> 411588 (-0.18%); split: -0.20%, +0.03%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38321>
 2025-11-10 18:30:42 +00:00
Ian Romanick
3e0c9ad316 nir/opt_if: Conditionally do not propagate constants through bcsel 
In some cases propagating through a bcsel may be harmful. If the bcsel
uses are unlikely to be eliminated in both branch of an if statement,
propagating through it may result in extra moves for phi instructions
and extended live ranges.

v2: Fix missing parameter in call. Noticed by Rhys. I fixed this on the
test machine, but I must have forgotten to propagate the change back to
my dev machine.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38321>
 2025-11-10 18:30:41 +00:00
Ian Romanick
a3b6d05a3b nir/opt_if: Specify which branches are valid for evaluate_if_condition 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38321>
 2025-11-10 18:30:41 +00:00
Marek Olšák
0216f09e45 nir/lower_interpolation: check IO location correctly 
Vangogh timed out.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38337>
 2025-11-10 16:44:36 +00:00
Sergi Blanch Torne
9e63a8a5d0 Revert "ci: disable Collabora's farm due to maintenance" 
This reverts commit a21cd9d60c.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38344>
 2025-11-10 14:24:01 +00:00
Ahmed Hesham
6901bb0c6c panfrost/lima/panvk: Define a common vendor ID 
Rusticl reports `CL_DEVICE_VENDOR_ID` using the `vendor_id` property
defined in Panfrost. The value is not set so a `0` is reported
instead.

Initialise the value to `0x13B5`, which is Arm's PCI vendor ID.

Add the definition in `lib/pan_props.h` so it can be shared with
Gallium Lima, Panfrost and PanVK.

Signed-off-by: Ahmed Hesham <ahmed.hesham@arm.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38283>
 2025-11-10 14:01:40 +00:00
Valentine Burley
e91832739b venus/ci: Add missing Collabora farm rules to ANV jobs 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38348>
 2025-11-10 12:47:26 +00:00
Patrick Lerda
ae049f6fea r600: limit pre-evergreen predicate ready size 
With the current stack configuration the rv770 seems to be unable
to go beyond three with the "vs-output-array-float-index-wr-before-gs.shader_test"
test. Anyway, the value four seems to be sufficient for the other tests.

This issue was triggered on rv770, for instance, with:
"piglit/bin/shader_runner tests/spec/glsl-1.50/execution/variable-indexing/gs-output-array-float-index-wr.shader_test -auto -fbo"
"piglit/bin/shader_runner tests/spec/glsl-1.50/execution/variable-indexing/vs-output-array-float-index-wr-before-gs.shader_test -auto -fbo"

Fixes: 713edb5998 ("r600/sfn: handle the IF predicate in the scheduler")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38213>
 2025-11-10 12:25:38 +00:00
Karol Herbst
92a4ae0ab2 rusticl/spirv: preserve signed zeroes by default 
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38327>
 2025-11-10 10:52:56 +00:00
Karol Herbst
df344f12cc rusticl/kernel: take no kernel_info reference inside the launch closure 
Otherwise patterns like this wouldn't work:

clCreateKernel(prog)
clEnqueueNDRangeKernel
clReleaseKernel
clBuildProgram(prog)

Fixes: bb2453c649 ("rusticl/kernel: move most of the code in launch inside the closure")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38327>
 2025-11-10 10:52:56 +00:00
Karol Herbst
c0f0baeaca rusticl/queue: fix error code for invalid sampler kernel arg 
Fixes: 5795ee0e08 ("rusticl: translate spirv to nir and first steps to kernel arg handling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38327>
 2025-11-10 10:52:56 +00:00
Karol Herbst
e98abe35c0 rusticl/queue: fix error code for invalid queue properties part 2 
Fixes: 2c202eb787 ("rusticl: verify validity of property names and values")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38327>
 2025-11-10 10:52:56 +00:00
Karol Herbst
e83400cab2 rusticl/queue: fix error code for invalid queue properties part 1 
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38327>
 2025-11-10 10:52:56 +00:00
Lucas Fryzek
a824754de0 lvp: Enable VK_FORMAT_R4G4B4A4_UNORM_PACK16 
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36558>
 2025-11-10 10:10:07 +00:00
Eric Engestrom
f689322d27 ci: track src/android_stub/ changes 
Fixes: 932f51d593 ("ci: Include enough Android headers to let us compile test EGL")
Suggested-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38346>
 2025-11-10 09:27:07 +00:00
Eric Engestrom
2ec3e536fd ci: track src/c11/ changes 
It's used by mesa_util, so let's just consider changes to it can affect
any job.

Fixes: b2ddec4e98 ("c11: Implement c11/time.h with c11/impl/time.c")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38346>
 2025-11-10 09:27:07 +00:00
Erik Faye-Lund
d607082b90 radeonsi/ci: document flake 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38345>
 2025-11-10 09:13:07 +00:00
Lionel Landwerlin
c478b6355a anv/blorp/iris: rework Wa_14025112257 
Drivers already have to track this workaround, so remove the logic
from Blorp and let the driver manage this.

Also in Anv don't accumulate this workaround, emit it directly in
place right after COMPUTE_WALKER. Accumulating can be problematic when
you want to dispatch concurrent compute shaders that do not need any
cache flush interaction (typical example with the internal
simple_shader framework).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3e0ad0176b ("anv: Emit state cache invalidation after every compute dispatch")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38306>
 2025-11-10 08:57:06 +00:00
Christian Gmeiner
0c31313b6e etnaviv: Disable trilinear filtering for shadow samplers 
The Vivante GPUs have a hardware bug where trilinear filtering
(MIP=LINEAR) produces incorrect results when used with depth/stencil
textures that have shadow comparison enabled, leading to GPU hangs.

Work around this by forcing MIP=NEAREST for depth/stencil formats,
downgrading from trilinear to bilinear filtering as done by binary blob
too.

Fixes dEQP-GLES3.functional.texture.shadow.*.linear_mipmap_linear.*
except DEPTH32F ones on all GPUs I have access to.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38308>
 2025-11-10 08:20:53 +00:00
Sergi Blanch Torne
a21cd9d60c ci: disable Collabora's farm due to maintenance 
Planned downtime in the farm:
* Start: 2025-11-10 08:00 UTC
* End: 2025-11-10 14:00 UTC

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37938>
 2025-11-10 07:09:36 +00:00
spencer-lunarg
f8e5e7cd7d lavapipe: Fix crash when using zero queues 
When using VK_KHR_maintenance9 the user can pass a null pointer
to VkDeviceQueueCreateInfo and we will create a dummy queue for
them.

Tested with new dEQP-VK.pipeline.no_queues.*
https://gerrit.khronos.org/c/vk-gl-cts/+/18717

Signed-off-by: spencer-lunarg <spencer@lunarg.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38288>
 2025-11-10 02:10:43 +00:00
Dave Airlie
179e744f75 c11/threads: fix build on c23 
C23/glibc is now including once_init in stdlib.h

https://patchwork.sourceware.org/project/glibc/patch/78061085-f04a-0c45-107b-5a8a15521083@redhat.com/#213088

Just fix up our use of it.

Cc: mesa-stable
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38298>
 2025-11-10 07:01:50 +10:00
Vinson Lee
1889f1a779 gfxstream: Fix GfxStreamVulkanMapper.cpp build error 
../src/gfxstream/guest/platform/kumquat/vulkan-mapper/GfxStreamVulkanMapper.cpp: In static member function ‘static GfxStreamVulkanMapper* GfxStreamVulkanMapper::getInstance(std::optional<DeviceId>)’:
../src/gfxstream/guest/platform/kumquat/vulkan-mapper/GfxStreamVulkanMapper.cpp:208:30: error: ‘os_get_option’ was not declared in this scope
  208 |         const char* driver = os_get_option(VK_ICD_FILENAMES);
      |

Fixes: 222b85328e ("mesa: replace most occurrences of getenv() with os_get_option()")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38331>
 2025-11-09 03:10:37 +00:00
Yiwei Zhang
894c47e384 pps/meson: minor refactor for pps_deps 
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38332>
 2025-11-08 18:39:00 -08:00
Yiwei Zhang
07a182a4bc pps/meson: amend missing util deps for os_get_option usage 
..otherwise -Dperfetto=true fails to build

Fixes: 222b85328e ("mesa: replace most occurrences of getenv() with os_get_option()")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38332>
 2025-11-08 18:38:52 -08:00
Karol Herbst
87550fc657 st/interop: fix fence leak 
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14050
Fixes: 1396dc1c38 ("mesa/st, dri2, wgl, glx: Modify flush_objects interop func to export a fence_fd")
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38310>
 2025-11-08 18:22:41 +00:00
Mel Henning
6e936ebc9c docs/nvk: Fix description of supported GPUs 
This description was incorrect in that it impiled we supported Hopper
and Blackwell A, which is not currently the case (see nvk_is_conformant
in nvk_physical_device.c).

Fixes: edd0cb6d56 ("docs/nvk: Update hardware support")
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38320>
 2025-11-08 17:23:58 +00:00
Mel Henning
c33e278fc0 nak/nvdisasm_tests: Skip SM70 on cuda 13 
cuda 13 drops support for sm70, including nvdisasm support. This matches
the default sm list to the detected nvdisasm version.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38322>
 2025-11-08 17:08:10 +00:00
Mel Henning
31e47c178d nak/nvdisasm_tests: Turn sm_list() into a function 
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38322>
 2025-11-08 17:08:10 +00:00
Faith Ekstrand
f1cb63a21d nil: Add support for Blackwell 8 and 16-bit modifiers 
Backport-to: 25.2
Reviewed-by: James Jones <jajones@nvidia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36336>
 2025-11-07 23:00:31 +00:00
Faith Ekstrand
3247452b2c drm-uapi: Import the new NVIDIA modifiers 
Imported from kernel commit eef295a850820 of drm-misc-fixes

Backport-to: 25.2
Reviewed-by: James Jones <jajones@nvidia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36336>
 2025-11-07 23:00:31 +00:00
Sagar Ghuge
14194e59a4 anv: Drop unwanted untyped flush for AS query 
CmdWriteAccelerationStructuresPropertiesKHR writes the data with MI
commands, we no longer dispatch shaders to write the properties.
As a result, we don't need to flush untyped cache.

Fixes: f0e18c475b ("intel: remove GRL/intel-clc")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38291>
 2025-11-07 22:04:25 +00:00
Ian Romanick
4687bd43d2 vulkan: Fix incorrect assert 
You can have a group with 0 shaders in it. See also febe90e109
("vulkan: remove incorrect assert"). Fixes assertion failure while
compiling fossils/q2rtx/q2rtx-rt-pipeline.976f4ab1c0fee975.1.foz on
Intel platforms.

Fixes: e05a9b77b6 ("vulkan/runtime: split rt shaders hashing from compile")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38318>
 2025-11-07 21:10:14 +00:00
Benjamin Cheng
82d944b388 radv/video: Fix dummy DPB addresses 
This fixes the VVL PositiveVideoDecodeAV1.* tests, which trigger error
concealment. These DPB addresses would not be normally used, but get
used by the error concealment path.

Fixes: d103b76ad6 ("radv/video: add VK_KHR_video_decode_av1 support.")
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38311>
 2025-11-07 18:16:48 +00:00
Danylo Piliaiev
9c4d2a1f51 tu: Add a reason for concurrent binning disablement to RP tracepoint 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38258>
 2025-11-07 17:50:03 +00:00
Danylo Piliaiev
6b0df4b01a tu: Add concurrent_binning_barrier tracepoint 
Makes easy to spot the synchronization points for CB.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38258>
 2025-11-07 17:50:03 +00:00
Dylan Baker
829ff578e4 docs: update calendar for 25.3.0-rc4 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38309>
 2025-11-07 17:44:24 +00:00
Dylan Baker
678827cc43 docs: update calendar for 25.3.0-rc3 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38309>
 2025-11-07 17:44:24 +00:00
Dylan Baker
e3996c3379 docs: update calendar for 25.3.0-rc2 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38309>
 2025-11-07 17:44:23 +00:00