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Author SHA1 Message Date
Pierre-Eric Pelloux-Prayer 41d22eb68e radeonsi: inhibit clockgating when using SQTT 
Ported from PAL.

Fixes: 07c1504d1b ("radeonsi: implement SQTT support")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8480>
 2021-01-19 09:52:08 +01:00
Iago Toral Quiroga a46547671b v3dv: only update uniforms for dirty descriptors if stage has descriptors 
If we have dirty descriptor set state we have to update our uniform
data to reference the new resources such as addresses for textures
or UBOs. This is known to have a high CPU cost, so we want to limit
this as much as we can.

It is a common rendering pattern in applications to render many objects
using the same pipeline, but modifying the descriptor sets bound to update
textures, UBOs, etc. In this scenario, we would be incurring in unnecessary
uniform stream updates for stages that don't access descriptor sets at all.

This change makes it so we track which shader stages in a pipeline
use descriptor set state and skips updating uniform streams for them
when dirty descriptor set state is the only reason requiring us to
generate new uniform streams for a draw call.

v2: reuse shader stage information from the pipeline set layouts
    to track shader stages that use descriptor state.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8555>
 2021-01-19 08:07:57 +00:00
Samuel Pitoiset c3ac6f7cd7 radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9 
This restores the previous logic because L2 coherency was fully
implemented. It appears that flushing L2 metadata with a CS_DONE
event hangs.

This fixes GPU hangs with Monster Hunter World.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8566>
 2021-01-19 07:47:34 +01:00
Vinson Lee 3e6b37a954 nv50/ir: Initialize DataArray members in constructor. 
Fix defects reported by Coverity Scan.

uninit_member: Non-static class member array is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member arrayIdx is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member baseAddr is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member arrayLen is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member baseSym is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member vecDim is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member eltSize is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member file is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member regOnly is not initialized in this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7764>
 2021-01-18 18:12:22 -08:00
Bas Nieuwenhuizen c4ea4e026b radv: Add a trivial implementation of VK_KHR_deferred_host_operation 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8545>
 2021-01-19 01:25:38 +01:00
Marek Olšák 290dcb26ae mesa: fix alpha channel of ETC2_SRGB8 decompression for !bgra 
If software decompression is used for ETC2, the alpha channel
for sRGB8 textures would be set only if BGRA is true.

Fixes: e5604ef78b "st/mesa/i965: Allow decompressing ETC2 to GL_RGBA"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8529>
 2021-01-18 17:18:20 -05:00
Icecream95 5eb39dd95f pan/bi: Iterate from zero when setting RA interference 
It is now valid for a node to have an index of zero.

Fixes: 39aa8c4a5a ("pan/bi: Switch to new IR")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig a63960b7f3 pan/bi: Fix printing of node 0 
Fixes: 1893a3805e ("pan/bi: Generate instruction printer")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig 3a16ab84e2 pan/bi: Fix RA of node 0 
Fixes: 39aa8c4a5a ("pan/bi: Switch to new IR")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig 92461a1133 pan/bi: Fix 64-bit SSBO addresses 
Fixes: 9c7efc4510 ("pan/bi: Add intrinsic emits for builder")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 a8c91f15f0 pan/mdg: Fix spilling when scratch memory is used 
Add the tls_size from NIR before spilling so that it doesn't alias
with spill slots.

Fixes: 152bc5d15e ("pan/mdg: Support loads and stores to scratch memory")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 6f0eff548c pan/bi: Implement packing ops between 32-bit vec1 and 16-bit vec2 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 c9c637a707 pan/bi: Implement ihadd/irhadd operations 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 591ccbcf47 pan/bi: Implement saturated add/sub operations 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 7258b4b48d panfrost: Set TLS for compute jobs 
Fixes CL programs using scratch storage, such as the Piglit test
i32-stack-array.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 3f7e7495fc pan/bi: Lower umul_high 
Also lower uadd_carry, which the mul_high lowering generates.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 2e372d0c3b pan/bi: Add w0 to the 'h01' swizzle bucket 
A number of instructions, such as LOAD.i8, use this swizzle in the XML.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 2ec0897b11 pan/mdg: Allow 64-bit src_bitsize for comparison operations 
Fixes Piglit test attributes.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 b5d6e5049f pan/mdg: Don't reorder loads/stores past each other 
Fixes Piglit test local-memory.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 24fcc032ef pan/mdg: Limit int64 vectorization 
Previously, nir_opt_vectorize was sometimes vectorizing 64-bit
load_const instructions to vec4.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 f0109e9ac0 panfrost: Assert on sysval overflow 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 24867386ee panfrost: Add a sysval for local_work_dim 
Fixes Piglit test get-work-dim.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 f5a35918db panfrost: Add a sysval for local_group_size 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 76fa57d195 pan/bi: Use pan_nir_lower_64bit_intrin 
The intrinsics covered by the pass are implemented by reading 32-bit
registers, so there is no reason to keep them 64-bit.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 7c2308769b panfrost: Use the correct NIR options for OpenCL on Bifrost 
This is needed so that 64-bit operations are lowered properly.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 c82ab9b94a pan/bi: Improve unknown intrinsic error 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 56f753f8e2 panfrost: Set bifrost_props for compute shaders 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 c71d4d931e pan/bi: Implement load_kernel_input 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 f33694552d pan/bi: Implement load/store intrinsics 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 58cf95a637 pan/bi: Improve interoperability of the command-line disassembler 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 7c6aa5f49d pan/bi: Set compute lowering options 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 d267183829 pan/bi: Add some compute intrinsic loads 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 2a7c33bd9d pan/bi: Handle 64-bit pack and unpack operations 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95 f5c9a10f33 pan/bi: Lower 64-bit integers 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig f4d2b35ac8 pan/bi: Pipe scratch_size in from NIR 
Needs to be added to whatever we spill ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Ilia Mirkin 087ef91c85 nvc0: index_bias is now only set for indexed draws 
Fixes: cbdc00ac3a ("nouveau: fix handling draw info")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8539>
 2021-01-18 17:51:58 +00:00
Ilia Mirkin 111c0733ea cso: set index_bounds_valid = true for arrays draws 
The min/max indices are valid. Set the bit to true to indicate that.

Fixes glClear (+ clear_with_quads) on nouveau.

Fixes: 72ff53098c (gallium: add pipe_draw_info::index_bounds_valid)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reported-by: Simon Ser <contact@emersion.fr>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8546>
 2021-01-18 17:33:52 +00:00
Erik Faye-Lund 333730405d zink: handle NULL views in zink_set_sampler_views 
Passing NULL for the views parameter should be the same as passing an
array of NULL, according to the documentation. So let's respect that
detail.

This fixes a crash when using GALLIUM_HUD.

Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8564>
 2021-01-18 17:06:12 +00:00
Samuel Iglesias Gonsálvez b50b28cd33 turnip: disable UBWC on Z24_S8 MSAA images on A630 
Fixes GPU hangs in dEQP-VK.renderpass2.depth_stencil_resolve.* tests
on A630.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8381>
 2021-01-18 17:32:21 +01:00
Jason Ekstrand 63a431b81c anv: Add a trivial implementation of VK_KHR_deferred_host_operation 
This isn't actually capable of deferring anything; it just trivially
returns success.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7735>
 2021-01-18 10:09:51 -06:00
Bas Nieuwenhuizen af1aef10f9 radv: Do not use a pipe offset for aliased sparse images. 
Otherwise the offset might not match between the images that are
aliased.

Fixes: e553ea51e8 ("radv: Create sparse images.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4072
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8535>
 2021-01-18 11:12:45 +00:00
Michel Dänzer 23f2e77710 wsi/x11: Use get_screen_resources_current in wsi_x11_detect_xwayland 
get_screen_resources may trigger an active probe of display connections
in the X server, which may take significant time and/or result in log
file spam.

Fixes: b5268d532a "wsi/x11: Detect Xwayland"
Reported-by: Sylvain Bertrand <sylvain.bertrand@legeek.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8492>
 2021-01-18 10:03:32 +00:00
Marek Olšák b06f3c52bf radeonsi: trim the size of si_vgt_param_key and si_vgt_stages_key 
These are the minimum sizes we can use.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák f1e34f125d radeonsi: don't use si_get_vs_state in most places 
It's incorrect because si_get_vs_state returns gs_copy_shader for legacy
GS. It was harmless, but let's use si_get_vs, which is simpler.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák 4088b6f293 radeonsi: rearrange condition for streamout workaround on gfx7 and gfx8 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák eb22bd2072 radeonsi: get out of si_emit_vs_state early for blit vertex shaders 
They don't use current_vs_state.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák 73709143d2 radeonsi: remove MRT-draw-calls, spill-draw-calls, spill-compute-calls 
due to limited usefulness and overhead in si_draw_vbo.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák f2a5148701 radeonsi: make sctx->vertex_elements always non-NULL 
Bind a state with 0 vertex elements there.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák 961aa67adf radeonsi: add a specialized function for CP DMA L2 prefetch 
This radically simplifies the code to decrease CPU overhead in si_draw_vbo.
The generic CP DMA copy function is too complicated.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák 0eca4660a5 radeonsi: make cik_emit_prefetch_L2 templated and move it to si_state_draw.cpp 
This is a great candidate for a template. There are a lot of conditions
that are already templated in si_draw_vbo.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00