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Author SHA1 Message Date
Lionel Landwerlin 1e29a1a8c5 anv: add grl build dependency on entrypoints 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7446
Fixes: f3ddfd81b4 ("anv: Build BVHs on the GPU with GRL")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19007>
 2022-10-10 19:14:07 +00:00
Danylo Piliaiev 4eba6d71a8 tu: Lazily init VSC to fix dynamic rendering in secondary cmdbufs 
Dynamic renderpasses need vsc_prim_strm_pitch, vsc_draw_strm_pitch
values, and a correct BO. The easiest way to solve this is to
lazily init VSC when it is needed, and not at every cmdbuf
initialization.

Fixes CTS tests (when running with TU_DEBUG=gmem,forcebin):
 dEQP-VK.draw.dynamic_rendering.complete_secondary_cmd_buff.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18996>
 2022-10-10 18:31:15 +00:00
Danylo Piliaiev e70a2148e5 tu: Do not DCE unused output vars used for transform feedback 
Fixes CTS tests:
 dEQP-VK.transform_feedback.simple.multiquery_omit_write_1
 dEQP-VK.transform_feedback.simple.multiquery_omit_write_3

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19020>
 2022-10-10 18:12:04 +00:00
Rob Clark f6098fb4f5 gallium/u_threaded: Add optional call-id tracing 
If enabled, use a scoped trace to see where calls happen on frontend vs
where they are pushed down to driver.  This is much lighter weight than
printf based tracing, but would still be an extra few instructions even
if perfetto tracing isn't active, so it is not enabled by default.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
 2022-10-10 17:47:21 +00:00
Rob Clark 81925e2cc7 gallium/u_threaded: Add some atrace/perfetto 
Use the MESA_TRACE_BEGIN/END() macros which will generate perfetto
traces (if perfetto is enabled) otherwise atrace (if android build), in
either case creating track events which will show up on the frontend
thread in a perfetto trace, giving visibility into where syncs happen.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
 2022-10-10 17:47:21 +00:00
Thomas Debesse 6d5921c623 nv50: call nir_lower_flrp 
Fix #7432: unknown nir_op flrp assertion

This copy-pastes src/gallium/drivers/radeonsi/si_shader_nir.c

The lower_flrp16 value differs given chipset >= NVISA_GV100_CHIPSET.

Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19003>
 2022-10-10 17:22:49 +00:00
pal1000 ed2743eae5 clc/clover: Link clang statically when shared-llvm is disabled 
Makes things easier to handle when aiming for a static build

Cc: mesa-stable

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18117>
 2022-10-10 12:20:30 +00:00
Erik Faye-Lund 55f6a2bb51 gallium: normalized_coords -> unnormalized_coords 
A lot of code zero-initializes pipe_sampler_state, and sets the states
the non-zero fields manually. This means that normalized_coords is the
"default" setting.

However, setting normalized_coords to true isn't allways allowed, and
we'd need to check PIPE_CAP_TEXRECT first. So it's not really the ideal
default here. There's recently been found quite a bit of bugs in this
area, where the state-tracker didn't properly lower texrects.

Let's switch this around to avoid more bugs like this in the future.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18971>
 2022-10-10 10:20:02 +00:00
Filip Gawin 4e7b9aaa06 r300: don't use smooth line if not requested 
Makes these tests passing:
dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.line_loop,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.line_strip,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.lines,UnexpectedPass
dEQP-GLES2.functional.rasterization.primitives.lines_wide,UnexpectedPass

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18979>
 2022-10-10 06:08:28 +00:00
Timothy Arceri 98944b327b util/radeonsi: enable zerovram workaround for Exanima 
The issue is very intermittent and can sometimes work fine
without the workaround but turning it on seems to resolve
any issues.

Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449

Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18935>
 2022-10-10 11:19:26 +11:00
Timothy Arceri 3200b5c46b util/conf: enable init to zero workaround for Exanima 
Fixes rendering issues on llvmpipe.

Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6449

Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18935>
 2022-10-10 11:16:22 +11:00
Lionel Landwerlin 091b5b08d4 pps: enable track_event in intel.cfg 
Take the opportunity to prune some ftraces that are not that useful
and fill the buffer pretty fast.

Record time is bumped to 1.2s

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18930>
 2022-10-09 22:39:53 +03:00
Konstantin Seurer e68adf19bc radv/rra: Transcode nodes recursively 
Instead of relying on a certain BVH layout, this patch traverses the BVH
from the root node which gets rid of any layout requirements.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18967>
 2022-10-09 17:39:31 +00:00
David Heidelberg 0c6c30d211 ci: uprev DXVK to 1.10.3 
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18888>
 2022-10-08 16:36:36 -05:00
Rob Clark 27aa172012 isaspec: Fix out of date comment 
Assembler support has existed for a long time.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:29 +00:00
Rob Clark c0cdc148f4 freedreno: Add perf-debug trace 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:29 +00:00
Rob Clark f6f72b5629 freedreno/drm: Don't call kernel with no ops 
When called with FD_BO_PREP_FLUSH as the only op bit set, the intention
is to only sync with the submit-queue.. we shouldn't be calling down to
the kernel (where op==0 gets interpreted as MSM_PREP_READ).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:29 +00:00
Rob Clark 6dcc524035 freedreno: Use TC cpu-storage to shadow buffers 
We still use the shadow path for non-buffer updates, where TC isn't
playing any tricks.  But for correctness we need to use the cpu-
storage approach, instead of buffer shadowing, otherwise we can race
with the frontend thread for PIPE_MAP_UNSYNCHRONIZED access.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7262
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
 2022-10-08 14:25:28 +00:00
Thomas Debesse 3aa76e6a05 r600: info.stage MESA_SHADER_KERNEL as MESA_SHADER_COMPUTE 
Fixes:

src/gallium/drivers/r600/sfn/sfn_nir.cpp:832: int r600_shader_from_nir(r600_context*, r600_pipe_shader*, r600_shader_key*): Assertion `shader' failed.

karolherbst said:

> long term r600 should implement PIPE_CAP_SHAREABLE_SHADERS

Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18963>
 2022-10-08 11:44:52 +00:00
Thomas Debesse 98cace5224 r600: set clear_buffer = u_default_clear_buffer 
Fixes:

thread '<unnamed>' panicked at 'Context missing features. This should never happen!', ../src/gallium/frontends/rusticl/mesa/pipe/context.rs:44:13

Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18962>
 2022-10-08 11:36:41 +00:00
Konstantin Seurer 505dd284c1 radv: Remove main_loop_case_visited 
Totals from 7 (14.00% of 50) affected shaders:
CodeSize: 219168 -> 216732 (-1.11%)
Instrs: 40211 -> 40040 (-0.43%)
Latency: 963520 -> 961498 (-0.21%)
InvThroughput: 221435 -> 220974 (-0.21%)
Copies: 5634 -> 5562 (-1.28%)
PreSGPRs: 387 -> 380 (-1.81%)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18929>
 2022-10-08 09:44:50 +00:00
Konstantin Seurer d4345ec4d2 radv: Use cache_uuid for accel struct compatibility 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18938>
 2022-10-08 09:23:55 +00:00
Dave Airlie 12efb83ae8 gallivm/sample: refactor multisample offset calcs code. 
Just consoldiate this

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18264>
 2022-10-08 09:56:50 +10:00
Dave Airlie b4f132b2dd gallivm/nir: drop some unused struct members. 
These weren't used in the nir paths.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18264>
 2022-10-08 09:56:46 +10:00
Dave Airlie c457e1f0e4 gallivm/sample: move some first_level/last_level calcs out 
There were a fair few instances of first/level dynamic state getting,
these could be moved up a level or two and made more common.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18264>
 2022-10-08 09:56:18 +10:00
Daniel Stone 3052d30dc2 CI: Re-enable Collabora devices 
Friday maintenance is done.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18998>
 2022-10-07 18:38:45 +00:00
Erik Faye-Lund b666c203ee gallium/u_threaded_context: remove stale comment 
We're now using PIPE_SHADER_MAX_SAMPLER_VIEWS, so this advice is
outdated.

Fixes: 620c5e9dd0 ("gallium/u_threaded_context: Use PIPE_MAX_SHADER_SAMPLER_VIEWS for sampler_buffers")
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18973>
 2022-10-07 17:06:58 +00:00
Sathishkumar S 12acee17fa frontends/va: reallocate surface for yuv400/yuv444 picture 
reallocate the surface appropriately based on the mjpeg sampling factor

v2:
use macros for mjpeg sampling factors (Ruijing Dong)
indentation fix (Thong Thai)

v3:
add comments to mention workaround of reallocation (Boyuan Zhang)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
 2022-10-07 15:14:39 +00:00
James Zhu 3e2f7905a6 radeonsi/vcn: enable jpeg decode of yuv444 and yuv400 
v2: set third plane offset only for 3 plane formats (Boyuan Zhang)

Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
 2022-10-07 15:14:39 +00:00
Sathishkumar S 6b933676cc frontends/va: support yuv 400/444 rt_formats in vaconfig 
check if vaprofile supports decode of yuv400 and yuv444 formats
and enable the corresponding rt_formats in vaconfig.

v2: use config->entrypoint as param instead of BITSTREAM (Sil Vilerino)

Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
 2022-10-07 15:14:39 +00:00
James Zhu d2c0ff1caf frontends/va: add support for yuv400 and yuv444 
v2: indentation fixes (Saleem)

Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
 2022-10-07 15:14:39 +00:00
James Zhu 9055ab9de3 util/format: add util format y8_400_unorm 
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
 2022-10-07 15:14:39 +00:00
Rajnesh Kanwal 791f187405 pvr: Add vulkan shader factory headers for Query and clear APIs. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
 2022-10-07 14:23:05 +00:00
Rajnesh Kanwal 0923de04ba pvr: Split pds compute shader create and upload code for reuse. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
 2022-10-07 14:23:05 +00:00
Rajnesh Kanwal b8d9afe75c pvr: Remove double error reporting. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
 2022-10-07 14:23:05 +00:00
Rajnesh Kanwal b03e73a024 pvr: Fix allocation size passed in pvr_cmd_buffer_alloc_mem. 
pvr_cmd_buffer_alloc_mem takes size in bytes. This change
fixes the invocations which assume it to be size in dwords.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
 2022-10-07 14:23:05 +00:00
Rajnesh Kanwal 0b694c2eb3 pvr: Fix heap type of availability_buffer allocation. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
 2022-10-07 14:23:05 +00:00
Rajnesh Kanwal c229916e38 pvr: Update buffer type macro names for consistency. 
Also changing struct pvr_descriptor_program_input to
struct pvr_pds_descriptor_program_input for consistency with
other similar structs defined in pvr_pds.h.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
 2022-10-07 14:23:05 +00:00
Simon Zeni 9e84fc73be mesa: unlock texture on error path in glEGLImageTargetTexStorageEXT 
The texture mutex was not properly unlocked on error path, leading to deadlocks

Fixes: 6a3f5c65 ("mesa: simplify st_egl_image binding process for texture storage")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7422

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18964>
 2022-10-07 09:52:31 -04:00
Diogo Ivo 941c70a28a nouveau: treat DRM_FORMAT_INVALID as implicit modifier 
Failing to allocate resources when DRM_FORMAT_INVALID
is passed as a modifier breaks tegra. Change this behaviour
so that this modifier is instead interpreted as a don't care,
allowing for the driver to choose an appropriate modifier internally.

v2: change nouveau instead of tegra (Thierry Rieding)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6693
Fixes: 129d83cac2 ("nouveau: Use format modifiers in buffer allocation")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18649>
 2022-10-07 13:35:52 +00:00
Gert Wollny 5cd3e39503 r600/sfn: Make sure all components are usable when lowering TF inputs 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny a34003d472 r600/sfn: Always enforce LDS operation order 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny 6b767f83c3 r600/sfn: Unroll loops after doing some optimizations 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny 3290978053 r600/sfn: assert on use of abs modifier in op3 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny e840645bb7 r600/sfn:explicitly initialize the memory pool 
This reduces the overhead of checking with each allocation
whether the pool is already initialized.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny 04aea1c0ba r600/sfn: Use the correct allocator for loop lists 
This fixes a memory leak.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny 4b7ae72c46 r600/sfn: Fix typo 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny 5bdbbe5399 r600/sfn: Delete final lowered nir shader early 
Since this is no longer needed we can as well free the
memory right away instead of waiting until the parent
shader is freed.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny 47bd2b7afc r600/sfn: Add peephole optimization for kill instructions 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00
Gert Wollny 6de40d17ba r600/sfn: don't propagate registers into conditional test 
We don't check whether the register is overwritten between the actual
conditional test and the test of the used result, so don't try to
optimize the evaluation of the conditional.

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
 2022-10-07 11:33:57 +02:00