Commit Graph

70797 Commits

Author SHA1 Message Date
Chad Versace 4085f1f230 anv/meta: Implement vkCmdResolveImage
This handles multisample color images that have a floating-point or
normalized format and have a single array layer.

This does not yet handle integer formats nor multisample array images.
2016-01-27 16:55:59 -08:00
Chad Versace 8cc1e59d61 anv/meta: Add func anv_meta_get_iview_layer()
This function is just meta_blit_get_dest_view_base_array_slice(), but
moved to the shared header anv_meta.h.

Will be needed by anv_meta_resolve.c.
2016-01-27 16:52:30 -08:00
Chad Versace 8cc6f058ce anv/gen8: Begin enabling pipeline multisample state
As far as I can tell, this patch sets all pipeline multisample state
except:
    - alpha to coverage
    - alpha to one
    - the dispatch count for per-sample dispatch
2016-01-27 16:52:27 -08:00
Chad Versace 57e4a5ea99 anv/gen8: Set multisample surface state 2016-01-27 16:48:20 -08:00
Chad Versace 9b3d660878 anv/meta: Merge anv_meta_clear.h into anv_meta.h
The header was too small.
2016-01-27 16:48:20 -08:00
Kenneth Graunke 32e4c5ae30 vtn: Make tanh implementation even stupider
The dEQP "precision" test tries to verify that the reference functions

   float sinh(float a) { return ((exp(a) - exp(-a)) / 2); }
   float cosh(float a) { return ((exp(a) + exp(-a)) / 2); }
   float tanh(float a) { return (sinh(a) / cosh(a)); }

produce the same values as the built-ins.  We simplified away the
multiplication by 0.5 in the numerator and denominator, and apparently
this causes them not to match for exactly 1 out of 13,632 values.

So, put it back in, fixing the test, but making our code generation
(and precision?) worse.
2016-01-27 15:34:50 -08:00
Jason Ekstrand 8f0ef9bbeb nir/opt_algebraic: Use a more elementary mechanism for lowering ldexp 2016-01-27 15:21:28 -08:00
Jason Ekstrand f7d6b8ccfe gen8/state: Fix QPitch for compressed textures on Broadwell 2016-01-27 15:12:42 -08:00
Jason Ekstrand 162c662585 anv/image: Use the entire image height for compressed meta blits 2016-01-27 15:12:42 -08:00
Nanley Chery 235abfb7e6 anv/image: Enlarge the image level 0 extent
The extent previously was supposed to match the mip at a given level
under the assumption that the base address would be that of the mip
as well.

Now however, the base address only matches the offset of the
containing tile. Therefore, enlarge the extent to match that of
phys_slice0, so that we don't draw/fetch in out of bounds territory.

This solution isn't perfect because the base adress isn't always at
the first tile, therefore the assumed valid memory region by the HW
contains some number of invalid tiles on two edges.
2016-01-27 15:12:42 -08:00
Jason Ekstrand 96cf5cfee1 anv/image: Minify before dividing by block dimensions 2016-01-27 15:12:42 -08:00
Jason Ekstrand 1bea1eff38 anv/meta: Don't double-call choose_buffer_format
This fixes all the renderpass tests
2016-01-27 15:12:42 -08:00
Nanley Chery dd22b5c914 anv/meta: Modify make_image_for_buffer()'s image
Always use a valid buffer format and convert the extent to units of
elements with respect to original image format.
2016-01-27 15:12:42 -08:00
Nanley Chery d3c1fd53e2 anv/image: Use custom VkBufferImageCopy for iview initialization
Use a custom VkBufferImageCopy with the user-provided struct as
the base. A few fields are modified when the iview is uncompressed
and the underlying image is compressed.
2016-01-27 15:12:42 -08:00
Nanley Chery 6a579ded87 anv: Add offset parameter to anv_image_view_init()
This is the offset of the tile that contains the mip specified by
isl_surf_get_image_intratile_offset_el(). Used to draw to/from the
specified mip.
2016-01-27 15:12:42 -08:00
Nanley Chery 4a0075feeb anv/meta: Calculate mip offset for compressed texture
This value will be used in a later commit.
2016-01-27 15:12:42 -08:00
Nanley Chery 1c87cb51be anv/meta: Disambiguate slice variable value
This will simplify the usage of
isl_surf_get_image_intratile_offset_el().
2016-01-27 15:12:42 -08:00
Nanley Chery 8c0c25abde gen8_state: use iview extent to program RENDER_SURFACE_STATE
When creating an uncompressed ImageView on an compressed Image, the
SurfaceFormat is updated to match the ImageView's. The surface
dimensions must also change so that the HW sees the same size image
instead of a 4x larger one.

Fixes the following error which results from running many VulkanCTS
compressed tests in one shot:
  ResourceError (vk.queueSubmit(queue, 1, &submitInfo, *m_fence):
  VK_ERROR_OUT_OF_DEVICE_MEMORY at
  vktPipelineImageSamplingInstance.cpp:921)

Makes all compressed format tests with a height > 1 pass.
2016-01-27 15:12:42 -08:00
Nanley Chery 3f01bbe7f3 anv/image: Scale iview extent by backing image
Aligns with formula's presented in Vulkan spec concerning CopyBufferToImage.
18.4 Copying Data Between Buffers and Images

This won't conflict with valid API usage, because:
1) Users are not allowed to create an uncompressed ImageView with a
compressed Image.
see: VkSpec - 11.5 Image Views - VkImageViewCreateInfo's Valid Usage box

2) If users create a differently formatted compressed ImageView with a
compressed Image, the block dimensions will still match.
see: VkSpec - 28.3.1.5 Format Compatibility Classes - Table 28.5
2016-01-27 15:12:42 -08:00
Nanley Chery 010ab34839 anv/meta: Set depth to 0 for buffer image in CopyBufferToImage()
The buffer image is a flat 2D surface. Each surface represents an
array/depth layer, therefore, the Z-offset is 0 when blitting.
2016-01-27 15:12:42 -08:00
Nanley Chery 2fb8b859f6 anv/meta: Use the uncompressed rectangle when blitting
For an uncompressed ImageView of a compressed Image, the
dimensions and offsets are all divided by the appropriate
block dimensions.

We are not yet using an uncompressed ImageView for a
compressed Image, but will do so in a future commit.
2016-01-27 15:12:42 -08:00
Nanley Chery c3546685ed i965: Update the surface_format table for ETC formats
Enable ETC support for BDW+. In Vulkan, an array lookup on
surface_format[] is used to determine HW support for certain
formats. In contrast, Mesa dynamically populates an array
which reports this information.
2016-01-27 15:12:42 -08:00
Nanley Chery 308ec0279b anv/image: Update usages of isl_surf_get_image_offset_sa 2016-01-27 15:12:42 -08:00
Nanley Chery 02629a16d1 isl: Add logical z offset to GEN4_2D surfaces
3D surfaces in Skylake are stored with ISL_DIM_LAYOUT_GEN4_2D. Any
delta in the logical z offset causes an equivalent delta in the
surface's array layer.
2016-01-27 15:12:42 -08:00
Chad Versace a6ecfe1dd3 isl/tests: Add some tests for intratile offsets
Test isl_surf_get_image_intratile_offset_el() in the tests:
  test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0
  test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0
2016-01-27 15:12:42 -08:00
Chad Versace 7ab0d2e2c0 isl: Add func isl_get_intratile_image_offset_el() 2016-01-27 15:12:42 -08:00
Chad Versace 18a83eaa8c isl/tests: Rename t_assert_offset()
Rename it to t_assert_offset_el(), clarifying that the offset in units
of surface elements, not samples.
2016-01-27 15:12:42 -08:00
Chad Versace fa08f95ff5 isl: Add func isl_surf_get_image_offset_el()
This replaces function isl_surf_get_image_offset_sa()
2016-01-27 15:12:42 -08:00
Chad Versace ea44d31528 isl: Fix row pitch for compressed formats
When calculating row pitch, the row's width in samples must be divided
by the format's block width. The commit below accidentally removed the
division.

    commit eea2d4d059
    Author: Chad Versace <chad.versace@intel.com>
    Date:   Tue Jan 5 14:28:28 2016 -0800
    Subject: isl: Don't align phys_slice0_sa.width twice
2016-01-27 15:12:42 -08:00
Chad Versace 45ecfcd637 isl: Add func isl_surf_get_tile_info() 2016-01-27 15:12:42 -08:00
Kenneth Graunke 9f954310e8 vtn: Fix atan2 for non-scalars.
The if/then/else block was bogus, as it can only take a scalar
condition, and we need to select component-wise.  The GLSL IR
implementation of atan2 handles this by looping over components,
but I decided to try and do it vector-wise, and messed up.

For now, just bcsel.  It means that we do the atan1 math even if
all components hit the quick case, but it works, and presumably
at least one component will hit the expensive path anyway.
2016-01-27 15:07:42 -08:00
Kenneth Graunke f92a35d831 vtn: Fix Modf.
We were botching this for negative numbers - floor of a negative rounds
the wrong way.  Additionally, both results are supposed to retain the
sign of the original.

To fix this, just take the abs of both values, then put the sign back.
There's probably a better way to do this, but this works for now.
2016-01-27 14:21:08 -08:00
Kenneth Graunke 4acfc9effb i965: Fix SIN/COS precision problems.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2016-01-27 13:56:54 -08:00
Kristian Høgsberg Kristensen b833e7a63c anv: Put back code to grow shader scratch space
This was lost in commit a71e614d33.
2016-01-27 11:36:56 -08:00
Kenneth Graunke 38a3a535eb anv: Update the device limits.
Fixes dEQP-VK.api.info.device.properties.  I haven't tested any others.
2016-01-26 23:09:45 -08:00
Jason Ekstrand d3607351fe gen7/cmd_buffer: SCISSOR_RECT structs are tightly packed
The pointer has to be 32-byte aligned, but the structs themselves are 2
dwords each, tightly packed.
2016-01-26 22:10:14 -08:00
Jason Ekstrand f2f03c5b65 anv/pipeline: Set MaximumVPIndex in 3DSTATE_CLIP 2016-01-26 21:52:59 -08:00
Jason Ekstrand dc3de6f8df anv/pipeline: Only lower input indirects if EmitNoIndirectInput is set 2016-01-26 21:45:21 -08:00
Jason Ekstrand 9ac624751e anv/formats: Use is_power_of_two instead of is_rgb to determine renderability 2016-01-26 20:29:16 -08:00
Jason Ekstrand 2af3acd061 HACK/i965/surface_formats: Mark A4B4G4R4 as being supported
The table has this marked as unsupported on all gens, but I don't really
believe that given how early it is in the table.  I've tested and it seems
to work on Broadwell.  The Bspec says that it sould be renderable on SKL+
but alpha blending is questionable.

Side note: We really need to audit the format table again.
2016-01-26 20:29:16 -08:00
Jordan Justen c20f78dc5d anv: Support swizzled formats.
Some formats require a swizzle in order to map them to actual hardware
formats.  This allows us to turn on two new Vulkan formats.
2016-01-26 20:29:16 -08:00
Jason Ekstrand 9bc72a9213 anv/image: Do swizzle remapping in anv_image.c
TODO: At some point, we really need to make an image_view_init_info that's
a flyweight and stop stuffing everything into image_view.
2016-01-26 20:23:59 -08:00
Jason Ekstrand 7d84fe9b1f HACK: Expose support for stencil blits
If someone actually tries to use them, they won't work, but at least we
don't fail to return format properties now.
2016-01-26 17:29:49 -08:00
Kenneth Graunke 32dcfc953e vtn: Delete references to IMix opcode.
This is being removed in SPIR-V.

Bugzilla: https://cvs.khronos.org/bugzilla/show_bug.cgi?id=15452
2016-01-26 17:02:35 -08:00
Ben Widawsky c5dc6cdf26 i965/skl: Utilize new 5th bit for gateway messages
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2016-01-26 15:44:48 -08:00
Jason Ekstrand a1ea45b857 genX/pipeline: Don't make vertex bindings with holes 2016-01-26 15:44:18 -08:00
Jason Ekstrand 7ef0d39cb2 anv/cmd_buffer: Put base_instance in the second component 2016-01-26 15:44:02 -08:00
Francisco Jerez 6840cc1513 anv/image: clflush surface state map in anv_fill_buffer_surface_state().
Some of its users had the required clflush on non-LLC platforms, some
didn't.  Put the clflush in anv_fill_buffer_surface_state() so we
don't forget.
2016-01-26 15:14:50 -08:00
Francisco Jerez fc7a7b31c5 anv/image: clflush the right state map in anv_fill_image_surface_state().
It was clflushing the nonrt_surface_state structure regardless of
which state structure was actually being initialized.
2016-01-26 15:14:50 -08:00
Francisco Jerez a50dc70e21 anv/image: Upload raw buffer surface state for untyped storage image and texel buffer access. 2016-01-26 15:14:50 -08:00