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Author SHA1 Message Date
Rhys Perry 405f3bf990 radv: disable 64-bit color attachments 
These work in some circumstances (dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc),
but I'm not sure if they work in all, blending certainly doesn't work and
this probably wasn't intended in the first place.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 01bd012edd ("amd: fix 64-bit integer color image clears")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Feng Jiang ad40073e4e meson: Rename dri-vdpau.dyn to dri.dyn 
File 'src/gallium/targets/dri-vdpau.dyn' is now shared by multiple
targets and not just VDPAU, so renamed it to 'dri.dyn' as suggested
by Marek Olšák.

Related link:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23177#note_2030493

Suggested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24569>
 2023-08-16 16:57:54 +00:00
Emma Anholt f0a362d5ba turnip: Move sysmem clears to the first subpass that uses them. 
This is a partial fix for the case where
VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT and the aliased attachment clears
the attachment that was last used in a previous subpass (we have to move
the stores to the last used subpass, as well).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt 21334e3b53 turnip: Move gmem clears and loads to the first subpass that uses them. 
This will help us share gmem space between attachments that aren't used at
the same time.  It's also a correctness fix for
VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT, because they're supposed to
happen at the first subpass using the attachment, not the start of the
renderpass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt 4cfd021e3f turnip: Save the renderpass's clear values in the cmdbuf state. 
For delaying clears to subpass begin time, I needed to save these until
later.  Turns out this cleans up a good bit of threading these values all
through the command buffer setup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt 139cc91697 turnip: Skip emitting empty CP_COND_REG_EXEC. 
If we ended up emitting no code to be conditionally run, then drop the
whole conditional exec packet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt c96b2cc511 turnip: Track the first/last subpass an attachment is used in. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt fce10ddf0f vulkan/util: Make multialloc succeed with 0 allocations. 
I wanted to use it for the attachments and clear values of a
vkCmdBeginRenderPass(), but both can be 0 count.  In that case, we would
end up with vk_default_alloc(0,0) because nothing had set the alignment,
and assertion fail instead of allocating 0 bytes.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Matt Turner d142c845d0 Revert "intel/fs: only avoid SIMD32 if strictly inferior in throughput" 
This reverts commit 6b494745be.

The logic is not entirely correct: the comparison is between two
static-analysis estimates of a dynamic system with variables that aren't
captured by the shader source, so using ">" will always have greater potential
to cause regressions whenever the performance difference between the two builds
is something not captured by the static model, no matter how much the model is
improved.

Reference: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9262
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24615>
 2023-08-16 14:56:15 +00:00
Lionel Landwerlin aebe584586 iris: ensure stalling pipe control before fast clear 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 87149cc545 ("blorp: update and move fast clear PIPE_CONTROLs to drivers")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24718>
 2023-08-16 13:59:46 +00:00
Christian Gmeiner bd1d322107 etnaviv: fix null pointer dereference 
Fixes: 734b15186b ("etnaviv: Stop passing around nir_dest")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24717>
 2023-08-16 13:17:23 +00:00
Erik Faye-Lund cff6c4d885 docs: upgrade bootstrap to 5.3.1 
Bootstrap 5.3.1 is out, implementing the color fix we introduced to make
dark-mode more readable. So let's update to that, and drop our override.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24670>
 2023-08-16 10:47:36 +00:00
Dor Askayo daa1f789b5 nouveau: add exported GEM handles to the global list 
Adding GEM handles to the global list is necessary to allow
maintaining a single reference count for handles that are shared
between multiple buffer objects.

Since exported handles can end up being shared with other buffer
objects, as in the case that drmPrimeHandleToFD() and gbm_bo_import()
are called externally to Mesa, they too must be added to the global
list.

Unfortunately, doing this properly requires a new libdrm API. Use
the best possible option for now.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9552

Signed-off-by: Dor Askayo <dor.askayo@gmail.com>
Acked-by: Karol Herbst <git@karolherbst.de>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24648>
 2023-08-16 10:28:22 +00:00
Andrew Randrianasulu d7cc19363f nv50/ir: Remove few nvc0 specific defines from nv50-specific header. 
Compile, and run-tested on nv92

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7259>
 2023-08-16 10:11:45 +00:00
Karol Herbst 7f63d2ebdb nv50: fix code uploads bigger than 0x10000 bytes 
The hardware has a max limit on how much data we can upload in one go via
the 2D engine. Just split the uploads up.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9571
Acked-by: M Henning <drawoc@darkrefraction.com>
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24706>
 2023-08-16 09:50:33 +00:00
Qiang Yu 8e13736222 radeonsi: remove unused arg of get_tcs_tes_buffer_address 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:36:37 +08:00
Qiang Yu 0e97fe38b7 radeonsi: part mode standalone tcs support aco compile 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:36:37 +08:00
Qiang Yu 59f4504d05 radeonsi: add si_aco_build_shader_part 
Now it only has tcs epilog build, will add more prolog/epilog to it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:36:37 +08:00
Qiang Yu 8631851b8f radeonsi: change si_fill_aco_options args 
Prepare to be shared with prolog/epilog generation which
does not have si_shader param.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:29 +08:00
Qiang Yu 04aadb32ad radeonsi: add si_get_tcs_epilog_args 
For shared with aco tcs epilog creation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:29 +08:00
Qiang Yu 8e0cff56f3 radeonsi: remove separate_prolog arg from prolog/epilog build 
It's always true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu b744405aa2 radeonsi: extract si_llvm_build_shader_part 
Prepare for aco code path.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu e797bd78c9 radeonsi: fill part mode tcs aco shader info 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu ac867af099 radeonsi: share si_get_tcs_out_patch_stride with aco 
Move it out of llvm to be shared with aco.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu 1001478a68 radeonsi: support upload multi part shader binary 
Need to split shader binary into exec and data part, then combine
exec and data of all shader parts separately. So const data symbols
in code need to be relocated.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu 85c0f31099 radeonsi: add exec_size to shader binary 
Used by aco binary to split exec code and const data when combine
multi part shader binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu 51a8479a51 aco: use semantic location as io temp index 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu 4c7fdebf9b ac/nir/tess: move tess factor output out of control flow 
For radeonsi aco compile which can't handle outputs without
nir_lower_io_to_temporaries().

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu 4756388038 aco,radeonsi: save const addr to symbol 
For radeonsi to relocation const data when combine multiple
shader parts to a single one. So the final shader binary will
begin with exec code of all parts then const data.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu facbd13df1 aco: skip scratch init when no scratch arg provide 
epilog does not use scratch so has no scratch arg.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu d3333609e6 aco: don't emit s_endpgm for tcs with epilog 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu b41d3e42f7 aco: add tcs epilog generation for radeonsi 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu a2484b20f9 aco: add pending_lds_access option for insert waitcnt 
For tcs epilog to add p_barrier at the beginning to sync
main shader part tess factor LDS write.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu 5cf6f4f9a7 aco: allow tcs with epilog to keep nir store output instruction 
Used to same tess factor outputs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu 5d05ae5df0 aco: add tcs end regs for epilog usage 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu 7c7062f8f9 aco: move jump to epilog out of ic_merged_wave_info 
TCS may be wrapped with if/else when merged shader. Jump
to epilog or end with regs should not be inside it.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu 85d9646288 aco: add p_end_with_regs pseudo instruction 
Used by radeonsi shader parts to pass args from one part to another.
It has variable number of operands to reserve fixed registers with
wanted value.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Julia Tatz a3549d7f7a aux/trace: trace video_buffer method return vals 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:30 +00:00
Julia Tatz 992ded3a3f aux/trace: unwrap refrence frames in picture_desc 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:30 +00:00
Julia Tatz ac9c2689a6 aux/trace: wrap video_codec & video_buffer 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:30 +00:00
Julia Tatz a5279f1ec5 aux/trace: add context video methods 
Preliminary support without wrapping video_codec or video_buffer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:30 +00:00
Julia Tatz ace894cff8 aux/trace: add screen video methods 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:30 +00:00
Julia Tatz 9d1da9ec20 aux/trace: fix set_hw_atomic_buffers method name 
Fixes: b2dc63ed8c ("aux/trace: Add pipe_context::set_hw_atomic_buffers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:30 +00:00
Julia Tatz 713437b2fc aux/trace: move trace_sample_view logic 
it's defined in tr_texture, so it makes sense and is more
re-usable to have it's logic there.
Also documented the magic number used for private refcounting

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:30 +00:00
Julia Tatz 9ff20e23fe aux/trace: deduplicate enum dump macro work 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:29 +00:00
Julia Tatz 87850734e7 aux/trace: skip multi-line comments in enums2names 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24482>
 2023-08-16 00:11:29 +00:00
Julia Tatz c4133a110d gallium/dri: fix dri2_from_names 
`createImageFromNames` uses fourcc, not dri_image_formats

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8547
Fixes: 433ca3127a ("st/dri: replace format conversion functions with single mapping table")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24597>
 2023-08-15 23:36:24 +00:00
José Roberto de Souza f7e39c6f85 intel/isl: Remove Wa_22011186057 
This is a ADL-P workaround of a pre-production stepping, with RPL-P
already being sold we can remove this workaround.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24699>
 2023-08-15 18:47:36 +00:00
José Roberto de Souza 4c06c736c5 intel/isl: Remove unknown workaround 
The way this workaround is implemented, it is being applied to all
gfx 12 platforms(TGL, ADL, RKL, RPL, DG1, DG2 and MTL) but it was
supposed to be fixed in TGL B0.
Unfortunately I did not found any workaround number that would match it.

But as all released platforms don't ship to customers with revision == 0
this workaround was never being applied and can be safely removed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24699>
 2023-08-15 18:47:36 +00:00
Faith Ekstrand b64da56b1a nir: s/nir_instr_ssa_def/nir_instr_def/ 
Generated by sed:

    sed -i -e 's/nir_instr_ssa_def/nir_instr_def/g' src/**/*.h src/**/*.c src/**/*.cpp

Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24703>
 2023-08-15 17:44:27 +00:00