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8401 Commits

Author SHA1 Message Date
Lionel Landwerlin 3f01071c79 intel/nir/rt: remove ray query mem hit writes at initialization 
This will not even be read by HW.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17396>
 2022-09-23 08:29:17 +00:00
Lionel Landwerlin f843bec7de intel/nir/rt: spill/fill the entire ray query data 
We need the traversal stack to saved/restored along with mem hits.
Total spill/fill is 256bytes.

We can potentially optimize this but we have to be very careful about
what state the query is in.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c78be5da30 ("intel/fs: lower ray query intrinsics")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17396>
 2022-09-23 08:29:17 +00:00
Lionel Landwerlin a88f725eea intel/nir/rt: fixup generate hit 
This function copies the potential hit from its memory location to the
committed hit location. A couple of fields got their bit offset wrong.

Fixes some CTS tests in dEQP-VK.ray_query.*

v2: Copy primitive/instance leaf pointers

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0465714790 ("intel/nir/rt: add more helpers for ray queries")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17396>
 2022-09-23 08:29:17 +00:00
Lionel Landwerlin f9dbb65e7f anv: add missing wokraround for texture cache invalidate 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18743>
 2022-09-22 23:45:16 +00:00
Iván Briano 14810f3498 intel/utrace: create the callback events for xfb trace points 
Fixes: 79c2f9e7cb ("anv: trace xfb queries")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7322

Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18738>
 2022-09-22 06:59:06 +00:00
Iván Briano ad89992ee1 anv: Set meshShaderQueries for mesh shader ext features 
v2 (Jordan): More descriptive commit message and fixes tag

Fixes: 9701b9098f ("anv: enable EXT_mesh_shader")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18735>
 2022-09-22 06:26:30 +00:00
José Roberto de Souza 89d2cdad37 intel/dev: Adjust prefetch_size values for MTL engines 
MTL has different CS prefetch sizes for each CS type.
So here replacing the cs_prefetch_size in intel_device_info struct
by a function that takes as argument the i915 engine class.

Fixes:
- func.cmd-buffer.small-secondaries.q0
- dEQP-VK.multiview.secondary_cmd_buffer.*
- Several other VK CTS tests that uses secondary_cmd_buffer

v2:
- renamed to intel_device_info_get_engine_prefetch() (Jordan)

v3:
- renamed to intel_device_info_calc_engine_prefetch()
- store each engine class prefetch in intel_device_info

BSpec: 45718
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18597>
 2022-09-22 02:14:47 +00:00
Lionel Landwerlin 7556ee1fe4 anv: add support for EXT_mutable_descriptor_type 
v2: Update docs/features.txt (Tapani)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18688>
 2022-09-21 13:34:20 +00:00
Lionel Landwerlin 369c12e5be anv: clear descriptorsets if AllocateDescriptorSets fails 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7285
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18719>
 2022-09-21 13:04:20 +00:00
Lionel Landwerlin 79c2f9e7cb anv: trace xfb queries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
 2022-09-21 12:38:34 +00:00
Lionel Landwerlin d53682e1a9 intel/utrace: make blorp tracepoints more readable 
With the operation name and some formats.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
 2022-09-21 12:38:34 +00:00
Lionel Landwerlin eac5e938c0 blorp: defined operations for debug purposes 
We add a mapping for blorp_op -> intel_snapshot

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
 2022-09-21 12:38:34 +00:00
Lionel Landwerlin b12d95f513 anv: add missing tracepoint 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3501a3f9ed ("anv: Convert to 100% dynamic rendering")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
 2022-09-21 12:38:34 +00:00
Marcin Ślusarz ac8020ebfd intel/compiler: add support for 8/16 bits task payload loads 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18501>
 2022-09-21 09:16:20 +00:00
Marcin Ślusarz ac581b30ec intel/compiler: refactor brw_nir_lower_mem_access_bit_sizes 
Change dup_mem_intrinsic return type.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18501>
 2022-09-21 09:16:20 +00:00
Marcin Ślusarz a31b8fa38b intel/compiler/task: use shared memory for small task payload loads & stores 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18501>
 2022-09-21 09:16:20 +00:00
Tapani Pälli 85fc1decf0 anv: remove primitive_topology from 3DPRIMITIVE calls 
Field is ignored on BDW+, 3DSTATE_VF_TOPOLOGY is used to set topology.

We still want to preserve topology information in state because
of other upcoming changes that require it.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18698>
 2022-09-21 04:42:42 +00:00
Tapani Pälli 8d66c45290 intel/common: clamp sample location coordinate range 
Applications may use out-of-range values, driver is responsible for
clamping to implementation-dependent sample location coordinate
range.

Without clamp we hit assert when packing 3DSTATE_SAMPLE_PATTERN if
application attempts to use bigger value than 0.9375.

 util_bitpack_ufixed: Assertion `min <= v && v <= max' failed.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18696>
 2022-09-21 04:05:45 +00:00
José Roberto de Souza 7d399a2e78 anv: Nuke cmd_parser_version 
This was only necessary for gen7 platforms that no longer support by
anv.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18601>
 2022-09-20 22:29:44 +00:00
José Roberto de Souza 6b36d20bb2 vulkan_hasvk: Nuke dead code around I915_ENGINE_CLASS_COMPUTE 
GPUs supported by this driver don't have I915_ENGINE_CLASS_COMPUTE,
so we can drop all this code.

v2:
- keeping anv_override_engine_counts()

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18601>
 2022-09-20 22:29:44 +00:00
Mike Blumenkrantz 0bf18cc483 anv: force inline more pipe flush functions 
yields increased ~33% draw throughput

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
 2022-09-20 20:53:22 +00:00
Lionel Landwerlin 39c6e4db25 anv: combine flushes in Draw/DrawIndexed/DrawIndirectByteCountEXT 
Based off a patch from zmike

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
 2022-09-20 20:53:22 +00:00
Lionel Landwerlin 1be09ae81a anv: don't export gfx state flushing helper 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
 2022-09-20 20:53:22 +00:00
Lionel Landwerlin 6aa2ddb9b6 anv: don't export flush_compute_state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
 2022-09-20 20:53:22 +00:00
Iván Briano f81c9badcc anv: populate rt shader groups if they were found in the cache 
If the pipeline does not use libraries and the shaders are all found in
the cache, we end up with empty groups and crash at pipeline emit time.

Fixes a bunch of tests under
dEQP-VK.pipeline.monolithic.shader_module_identifier.\*.ray_tracing\*

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18582>
 2022-09-20 20:03:49 +00:00
Marcin Ślusarz 37e78803d7 intel/compiler: use nir_lower_task_shader pass 
This implements task payload atomics in ANV.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16852>
 2022-09-20 18:04:29 +00:00
Marcin Ślusarz 3c96959bbc intel/compiler: print shader after successful brw_nir_lower_shading_rate_output 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18702>
 2022-09-20 17:23:45 +00:00
Marcin Ślusarz cfd1e5a91e intel/compiler: remove second shading rate lowering for mesh 
It's already called in brw_postprocess_nir and calling it the second time
actually breaks shading rate.

Initially, when I added this call here in 9acb30c8c4, I was testing it
on an internal tree, which didn't have brw_nir_lower_shading_rate_output call
in brw_postprocess_nir.

Fixes: 9acb30c8c4 ("intel/compiler: implement primitive shading rate for mesh")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18702>
 2022-09-20 17:23:45 +00:00
Marcin Ślusarz 037404b441 nir, anv, hasvk, radv: pull uses_wide_subgroup_intrinsics into shader_info 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
 2022-09-20 10:19:21 +00:00
Marcin Ślusarz de5b137a2d anv: small cleanup of anv_graphics_pipeline_compile 
Extract variables for things that are computed multiple times.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
 2022-09-20 10:19:21 +00:00
Marcin Ślusarz 06e0342a0d anv: add support for anv_assume_full_subgroups to task & mesh stages 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
 2022-09-20 10:19:21 +00:00
Tapani Pälli c184b49cf3 anv: remove vk_sample_locations_state from emit_multisample 
State for sample locations is not used within this function.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18669>
 2022-09-20 03:59:04 +00:00
Illia Polishchuk 74658b01d2 driconf/Intel: Add lower_depth_range_rate option workaround for Homerun Clash misrendering issue 
Intel has different Z interpolation float point rounding
than other mesa gpus
For example gl_Position.z = 0.0 will be interpolated to
gl_FragCoord.z = 0.5 for all gpus

gl_FragCoord = -0.00000001 will be interpolated to
gl_FragCoord.z = 0.4999999702 for Intel
and rounded to gl_FragCoord.z = 0.5 for other gpus

Games with LEQUAL depth func will fail depth test on Intel
and will pass it on other gpus in such case

This workaround lowers translated depth range
and several gl_FragCoord.z coords with extra small difference
will be translated to the same UINT16\UINT24\UINT32
value of an integer depth buffer

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7199

Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18412>
 2022-09-19 10:08:48 +00:00
Marcin Ślusarz dedd8affd8 anv: fix emission of primitive replication packet for mesh stage 
anv_pipeline_get_last_vue_prog_data (used by emit_3dstate_primitive_replication)
doesn't work for mesh stage.

Fixes: ae57628dd5 ("anv: Drop anv_pipeline::use_primitive_replication")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18495>
 2022-09-19 09:44:00 +00:00
David Heidelberg f380a2d63e ci/intel: drop glmark2 terrain trace 
See: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db/-/merge_requests/50

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18633>
 2022-09-18 18:51:14 +00:00
Thomas H.P. Andersen 74cebc5d5d hasvk: Switch to the common descriptor update template struct 
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
 2022-09-17 03:32:29 +00:00
Jason Ekstrand 94f8222dde anv: Switch to the common descriptor update template struct 
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
 2022-09-17 03:32:29 +00:00
José Roberto de Souza f4857591e1 intel/compiler/fs: Use DF to load constants when has_64bit_int is not supported 
This was already been done to gen7 platforms, so now extending to all
platforms without has_64bit_int.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18577>
 2022-09-14 19:32:43 +00:00
José Roberto de Souza daf0b67bc2 intel/compiler/fs: Fix compilation of shaders with SHADER_OPCODE_SHUFFLE of float64 type 
During the lower_regioning() optimization, required_exec_type() is
returning BRW_REGISTER_TYPE_UQ type when processing
SHADER_OPCODE_SHUFFLE instructions of type BRW_REGISTER_TYPE_DF but
MTL has float64 support but lacks int64 support causing shader
compilation to fail.

To fix that we could make required_exec_type() return
BRW_REGISTER_TYPE_DF in such case but SHADER_OPCODE_SHUFFLE virtual
instruction runs in the integer pipeline(inferred_exec_pipe()).

So here replacing the has_64bit check by has_64bit_int, this will
properly handle older and newer cases making this function return
BRW_REGISTER_TYPE_UD.
Then lower_exec_type() will take care to generate 2 32bits operations
to accomplish the same.

While at it also dropping the 'devinfo->verx10 == 70' check as
GFX7_FEATURES fall into the same category as MTL, has float64 but no
int64 support.

Fixes at least this crucible tests:
func.uniform-subgroup.exclusive.fadd64.q0
func.uniform-subgroup.exclusive.fmin64.q0
func.uniform-subgroup.exclusive.fmax64.q0

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18577>
 2022-09-14 19:32:43 +00:00
Tapani Pälli ddcd6b3834 anv: disable preemption on VFG, Wa_14015207028 for DG2 
This workaround disables batch level preemption for Polygon,
Trifan and Lineloop primitive topologies.

v2: cleanups (José)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>
 2022-09-14 10:01:23 +00:00
Tapani Pälli d5d4604aa6 intel/genxml: add VFG_PREEMPTION_CHICKEN_BITS register 
This can be used to disable batch preemption on DG2+ either
completely or with selected primitive topologies.

Commit adds bit explicitly for Polygon, Trifan and LineLoop
topologies for Wa_14015207028.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>
 2022-09-14 10:01:23 +00:00
David Heidelberg f2649b93e2 ci: performance traces: make use of no-perf label 
Traces with label `no-perf` will be skipped in performance testing.

This commit adds the yq tool, which preprocesses the traces.yml file
before sending it to the piglit.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
 2022-09-13 09:16:19 +00:00
David Heidelberg efc8eeaf7e ci/intel: convert traces to new YAML format 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
 2022-09-13 09:16:19 +00:00
Caio Oliveira e612f32e1a intel/compiler: Use brw_ud* helpers in thread payload code 
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira f019687d23 intel/compiler: Add a few more brw_ud* helpers 
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira 3272868218 intel/compiler: Make thread_payload struct abstract 
Each shader stage has its own struct and will instantiate it, so the
base class doesn't need to be instantiated anymore.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira 0b6e613de8 intel/compiler: Create and use struct for CS thread payload 
Move subgroup_id, that's only used by CS for verx10 < 125, as part of
the payload too -- even though is not, strictly speaking.

Note the thread execution of Task/Mesh is similar enough, so we make
their common struct inherit from cs_thread_payload.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira d8461e975a intel/compiler: Export brw_get_subgroup_id_param_index() 
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira 9de790760e intel/compiler: Create and use struct for Bindless thread payload 
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00
Caio Oliveira a70378f292 intel/compiler: Store start of ICP handles in GS thread payload struct 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
 2022-09-13 01:44:24 +00:00