3b48b7df1f
intel/blorp: Use a Meson dependency for blorp
...
Reviewed-by: Dylan Baker <dylan@pnwbakers.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27643 >
2024-02-16 00:08:42 +00:00
f733215c12
anv: enable query clear/copy using shaders on MTL/ARL
...
It seems like an L3 setting is different between DG2 & MTL, breaking
the L3 coherency with CS.
We can apply the same tile cache flush as we do on TGL for now until
we figure out how to configure L3 properly to avoid this.
Tested with :
$ query_clear_with_blorp_threshold=0 query_copy_with_shader_threshold=0 ./deqp-vk -n dEQP-VK.query_pool.*
to force the shader optimizations.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27597 >
2024-02-15 17:25:37 +00:00
c8fda63378
intel/blorp: Don't require specific prog_data type in callback
...
Make interface less dependent on brw types. If we care, later
might make sense to add a tagged union for the possible types here.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581 >
2024-02-15 10:29:18 +00:00
5992185c8d
intel/compiler: Merge intel_disasm.[ch] into corresponding brw files
...
Rename the functions to match the existing ones.
Acked-by: Dylan Baker <dylan@pnwbakers.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27579 >
2024-02-15 09:26:46 +00:00
5732c9d269
intel/compiler: Rename brw_cs_dispatch_info to intel_cs_dispatch_info
...
And move to the intel_shader_enums.h file.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475 >
2024-02-14 22:31:23 -08:00
c5b80de583
intel/compiler: Rename brw_vue_map to intel_vue_map
...
And move to the intel_shader_enums.h file.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475 >
2024-02-14 22:31:23 -08:00
7d85d2c7fd
intel/compiler: Rename DISPATCH_MODE_* enums to INTEL_DISPATCH_MODE_*
...
And move to the intel_shader_enums.h file.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475 >
2024-02-14 22:31:23 -08:00
aeda865b6d
intel/compiler: Rename BRW_TESS_* enums to INTEL_TESS_*
...
And move to the intel_shader_enums.h file.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475 >
2024-02-14 22:31:23 -08:00
26dd1f0bba
intel/compiler: Rename BRW_WM_MSAA_* enums to INTEL_MSAA_*
...
And move to the intel_shader_enums.h file.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475 >
2024-02-14 22:31:23 -08:00
29ee85c203
anv: Use intel_engines_supported_count()
...
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233 >
2024-02-14 17:29:54 +00:00
398bdb46ba
anv: Drop include to common/i915/intel_gem.h
...
Common code should not directly include KMD specific files.
At least there was no usage from symbols defined in this file.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233 >
2024-02-14 17:29:54 +00:00
e54638ddf5
anv: fix buffer marker cache flush issues on MTL
...
For some yet unknown reason the CS L3 coherency setting is different
on MTL than DG2.
Fixes issues in tests from the subgroup :
dEQP-VK.api.buffer_marker.*
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: c8e122a738tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27613 >
2024-02-14 13:45:46 +00:00
34078b67ed
anv: don't allocate aux padded BOs with host pointers
...
We can't allocate additional space with host pointers anyway. These
are already allocated pieces of memory by the application.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 646a7c864dhttps://gitlab.freedesktop.org/mesa/mesa/-/issues/10608
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27612 >
2024-02-14 11:51:33 +00:00
feb7cf82dc
anv: remove redundant asserts
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27611 >
2024-02-14 11:07:10 +00:00
29a6beb36e
anv: revert cache flushing changes for indirect commands
...
This reverts commit d699600da1https://gitlab.freedesktop.org/mesa/mesa/-/issues/10600
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27591 >
2024-02-13 09:47:32 +00:00
b52e25d3a8
anv: rewrite internal shaders using OpenCL
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:45 +00:00
41b2ed65e2
genxml: generate opencl packing headers
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:45 +00:00
c53a4711cb
anv: fix incorrect flushing on shader query copy
...
When doing query result copies in 3D mode, we're flushing the render
target cache, but the shader writes go through the dataport.
Fixes flakes/fails in piglit with shader query copies forced with Zink :
$ query_copy_with_shader_threshold=0 ./bin/arb_query_buffer_object-coherency -auto -fbo
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: b3b12c2c27kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:44 +00:00
c517088cf1
anv: factor out post submit queue debug code
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:44 +00:00
646a7c864d
anv: re-introduce BO CCS allocations
...
On Gfx12.0, CCS allocations have to be allocated per image because the
format of the image goes into the AUX-TT PTEs. The effect on memory
allocations is limited since the main surface granularity in the
AUX-TT PTE is 64KB.
On Gfx12.5, the granularity of the AUX-TT PTE is 1MB. This creates a
lot of waste in the application memory allocations. Fortunately the HW
doesn't care about the format put into the PTEs anymore. So it becomes
possible to have 2 images share the same PTE.
To implement this we bring back an earlier version of AUX-TT mappings
where we used to allocate additional CCS space at the end of the
VkDeviceMemory objects. On Gfx12.5, if the BO has additional CCS
space, we will now map the main surface to that space.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822 >
2024-02-12 21:00:27 +00:00
da6484a8a4
anv: use address helper to compute address u64 value
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822 >
2024-02-12 21:00:27 +00:00
7763e75eea
anv: move ALLOC_HOST_CACHED_COHERENT as define
...
That way gdb can decode the other flags when looking at the variables.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822 >
2024-02-12 21:00:27 +00:00
28ad2f488a
anv: Store host-located copy of NULL surface state for faster memcpy
...
Real null_surface_state is located in the GPU memory, so copying from
there will be slow for dGPUs.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10594
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27577 >
2024-02-12 17:48:15 +00:00
e0b4dfbbda
anv: don't unmap AUX ranges at BO delete
...
It is possible to free memory backing images before images are
destroyed :
VkFreeMemory:
"Memory can be freed whilst still bound to resources, but those
resources must not be used afterwards."
The spec leaves us the option to keep a reference on the associated
memory and free it only when all the bound resources have been
destroyed. Here we choose to free memory immediately.
One particular test in the CTS
(dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics)
does the following :
imgA = vkCreateImage()
imgB = vkCreateImage()
memA = vkAllocateMemory()
vkBindImageMemory(imgA, memA) # Aux mapping with ref count = 1
vkFreeMemory(memA) # Aux mapping removed, ref count = 0
memB = vkAllocateMemory() # Same address as memA
vkBindImageMemory(imgB, memB)
vkDestroyImage(imgA) # Removes the mapping of imgB-memB
vkQueueSubmit() # hang with pagefault in AUX-TT
The solution implemented in this change is to not do anything AUX-TT
related in vkFreeMemory(). This soluation has some consequences,
because a virtual memory address range freed and reallocated cannot be
rebound in the AUX-TT until all the associated resources have released
their AUX-TT mapping (to bring back the AUX-TT refcount of the range
to 0). This should still be better than keeping the memory allocated
through refcounting of the anv_bo.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 7b87e1afbchttps://gitlab.freedesktop.org/mesa/mesa/-/issues/10528
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27566 >
2024-02-12 15:37:18 +00:00
8b4259e69b
wsi/x11: Disable vk_xwayland_wait_ready by default on most drivers.
...
Venus is special and still requires extra waits.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no >
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27074 >
2024-02-10 11:47:22 +00:00
d699600da1
anv: reduce cache flushing for indirect commands on Gfx12.5+
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27257 >
2024-02-09 22:46:07 +00:00
3579413aed
anv: Switch to truly asynchronous VM binding in Xe KMD
...
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26805 >
2024-02-09 20:24:48 +00:00
f23395e2b9
anv: Start to use intel_bind_timeline
...
With this patch, VM binds remain synchronous in relation to vm_bind()
KMD backend calls. However, the syscalls required for VM bind is
reduce in 2(in the optimal cases), the syncobj create and destroy
syscall are replaced by he usage a timeline syncobj.
Next step will be make this completely asynchronous.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26805 >
2024-02-09 20:24:48 +00:00
964042d50c
anv/query: Follow MTL code paths on ARL
...
Ref: 0a52002a1cb3b12c2c27jordan.l.justen@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352 >
2024-02-06 21:23:19 +00:00
c1ffd0a037
anv/drirc: Extend option to disable FCV optimization to ARL
...
Ref: 01046cd6adjordan.l.justen@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27352 >
2024-02-06 21:23:19 +00:00
32800aa1d7
anv: enable VK_EXT_headless_surface on all platforms except Windows
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27448 >
2024-02-06 20:32:38 +00:00
0a44f6319e
anv,driconf: Add sampler coordinate precision workaround for AoE 4
...
AoE4 samples texture on the edge between texels, which can cause
unexpected texel to be returned, and cause misrenderings. This workaround
enables coordinate rounding even in NEAREST mode, which fixes the problem.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9864
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27337 >
2024-02-06 10:29:15 +00:00
5178ad761c
anv: flush tile cache independent of format with HIZ-CCS flush
...
Cc: mesa-stable
Fixes: ba87656079https://gitlab.freedesktop.org/mesa/mesa/-/issues/10420
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10530
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Tested-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27440 >
2024-02-05 21:50:26 +00:00
5ae2b4882a
blorp: implement Wa_16014912113 callback for drivers
...
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920 >
2024-02-05 13:50:58 +00:00
1693d0b857
anv: implement Wa_16014912113
...
When URB state for DS changes, we need to emit URB setup for VS with
256 handles and 0 for rest, commit this using a HDC flush before
setting real values.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920 >
2024-02-05 13:50:58 +00:00
a1b885b482
intel: refactor urb configuration, add intel_urb_config
...
Patch adds a structure holding urb configuration. This makes it nicer
to pass it around as example for blorp. We need to be able to sometimes
compare with last urb configuration to be able to implement some
workaround.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920 >
2024-02-05 13:50:58 +00:00
cc7400e49c
anv: report rotate subgroup feature bits
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27444 >
2024-02-05 11:20:28 +00:00
4fd4a6109d
anv: refactor to use DETECT_OS_ANDROID instead of ANDROID
...
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org >
Acked-by: Yonggang Luo <luoyonggang@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27374 >
2024-02-01 19:29:49 +00:00
1e80a426c2
anv: extend implicit fencing support for case requiring implicit write
...
This change extends the coverage to ANV being the producer while
consumer is hardware encoder backed by iHD. So we'd apply implicit write
to bos backing render target images, which is mostly aligned with
i915_batch_submit tracking of the bos being writtern to.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Matt Turner <mattst88@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27398 >
2024-02-01 18:53:28 +00:00
be3af5acf6
anv: optimize the implicit fencing support of external memory
...
Previously we apply implicit sync to all external memory, which is a bit
redundant since we only need it for the dedicated image scenario (media
image imported into Vulkan). This change optimizes just like that while
also excluding wsi which has its own way of synchronizing with the
compositor.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Matt Turner <mattst88@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27398 >
2024-02-01 18:53:28 +00:00
55ac9a08b5
anv: refactor wsi_memory_allocate_info handling
...
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Matt Turner <mattst88@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27398 >
2024-02-01 18:53:28 +00:00
a53af34664
anv: use workaround framework for Wa_22018402687
...
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27384 >
2024-01-31 21:24:14 +00:00
01636ee700
anv: Disable compression if we have concurrent sharing mode
...
If a resource is created with sharing mode CONCURRENT when multiple
queues are supported, we can't support the compression since we can't do
FULL_RESOLVE/PARTIAL_RESOLVE to construct the main surface data without
barriers.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27349 >
2024-01-31 19:28:12 +00:00
3d4ef6f983
intel/vulkan: assume() that we don't use "ISL_NUM_FORMATS"
...
Which coverity thinks will happen, even though we never return
ISL_NUM_FORMATS.
CID: 1559463
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27369 >
2024-01-31 18:59:16 +00:00
d0d2cf549b
anv/video: fix out-of-bounds read
...
Since STD_VIDEO_H265_CHROMA_QP_OFFSET_TILE_COLS_LIST_SIZE is 19.
Fixes: 8d519eb5Closes : mesa/mesa#10529
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27373 >
2024-01-31 08:24:22 +00:00
26c8f13ff5
vulkan: enable VK_KHR_shader_expect_assume
...
This implementation ignores the hints.
Acked-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27265 >
2024-01-30 19:09:42 +00:00
29d18f3ca9
anv: Fix typo in transition_color_buffer
...
Signed-off-by: Haihao Xiang <haihao.xiang@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27330 >
2024-01-30 07:39:01 +00:00
3b9466dd51
anv: fix transfer barriers flushes with compute queue
...
Transfer operation are implemented differently on the compute engine
and require a different kind of cache flush.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27233 >
2024-01-26 20:47:18 +00:00
9d31680e79
anv: retain ccs image binding address
...
Memory can be free before images it is bound to. When unmapping the
CCS range in the AUX-TT, we cannot rely on the anv_bo::offset field
because the anv_bo might have been freed.
Just save the mapping address/size and use those values at unmapping
time.
Fixes an assert on CI with :
dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: e519e06f4btapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27304 >
2024-01-26 17:29:31 +00:00
eead86ad8e
anv: rename aux_tt image field
...
We'll add more to the sub-struct
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27304 >
2024-01-26 17:29:31 +00:00
Caio Oliveira