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Author SHA1 Message Date
Konstantin Seurer
3aa3eb8ddd nir/opt_large_constants: Handle small float arrays 
Handles small arrays of integer, positive floats.

RADV fossils:

Totals from 65 (0.05% of 131205) affected shaders:
Instrs: 30001 -> 29936 (-0.22%); split: -0.39%, +0.18%
CodeSize: 165676 -> 164996 (-0.41%); split: -0.53%, +0.12%
Latency: 126873 -> 127178 (+0.24%); split: -0.29%, +0.53%
InvThroughput: 26640 -> 26895 (+0.96%); split: -0.48%, +1.44%
VClause: 425 -> 371 (-12.71%)
SClause: 982 -> 981 (-0.10%); split: -0.92%, +0.81%
Copies: 2072 -> 1939 (-6.42%); split: -6.52%, +0.10%
PreVGPRs: 1553 -> 1537 (-1.03%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Faith Ekstrand
e38522608f nir/opt_large_constants: Add Small constant handling 
Adds handling for constant arrays that can be lowered to
'(imm >> bit_index) & bit_mask' instead of constant loads.

RADV fossils:

Totals from 70 (0.05% of 131205) affected shaders:
Instrs: 31441 -> 31260 (-0.58%); split: -0.59%, +0.02%
CodeSize: 172104 -> 170568 (-0.89%)
VGPRs: 2608 -> 2616 (+0.31%)
Latency: 296687 -> 280859 (-5.33%); split: -5.34%, +0.00%
InvThroughput: 65491 -> 65696 (+0.31%); split: -0.11%, +0.42%
VClause: 671 -> 646 (-3.73%)
SClause: 1014 -> 964 (-4.93%)
Copies: 1742 -> 1564 (-10.22%); split: -10.51%, +0.29%
PreSGPRs: 2039 -> 2036 (-0.15%)
PreVGPRs: 2014 -> 2017 (+0.15%)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Faith Ekstrand
8ec0fdf017 nir/large_constants: Add read/write_const_values helpers 
The write helper is just pulling code we already have out into a helper
and flipping the order of the loop and the switch.  The read helper will
be useful in the next commit where we add small constant support.  This
keeps the two helpers right next to each other in the file where they're
easy to compare and we can ensure that they stay in sync.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Faith Ekstrand
7456ee0523 nir/large_constants: Use nir_component_mask_t 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9000>
 2023-08-16 23:36:29 +00:00
Mohamed Ahmed
783d59eec1 nil: Add support for G8B8_G8R8_UNORM and B8G8_R8G8_UNORM 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>
 2023-08-16 22:36:27 +00:00
Mohamed Ahmed
c7f109352d nvk: Enable MIDPOINT_CHROMA_SAMPLES_BIT for multi-planar formats only 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>
 2023-08-16 22:36:27 +00:00
Mohamed Ahmed
b9801a3c08 nvk: Enable SEPARATE_RECONSTRUCTION_FILTER_BIT for multi-planar formats only 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24614>
 2023-08-16 22:36:27 +00:00
Faith Ekstrand
4e2830c9ef nir: Clean up nir_op_is_vec() and its callers 
The nir_op_is_vec() helper I added in 842338e2f0 ("nir: Add a
nir_op_is_vec helper") treats nir_op_mov as a vec even though the
semanitcs of the two are different.  In retrospect, this was a mistake
as the previous three fixup commits show.  This commit splits the helper
into two: nir_op_is_vec() and nir_op_is_vec_or_mov() and uses the
appropriate helper at each call site.  Hopefully, this rename will
encurage any future users of these helpers to think about nir_op_mov as
separate from nir_op_vecN and we can avoid these bugs.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand
408929289a nir: Don't handle nir_op_mov in get_undef_mask in opt_undef 
It's unnecessary because earlier parts of the pass will ensure that a
mov of undef is turned into an undef.  It's also wrong because
nir_op_mov has different semantics from nir_op_vecN when it comes to how
sources map to destination components.

Fixes: 5f26c21e62 ("nir: Expand opt_undef to handle undef channels in a store intrinsic")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand
f9a17c6fef nir: Handle nir_op_mov properly in opt_shrink_vectors 
If the opcode is a mov, it falls into the nir_alu_src_is_trivial_ssa
case, not the vec case.

Fixes: 94eff7ccd8 ("nir: shrink phi nodes in nir_opt_shrink_vectors")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand
9bcc9597a5 nir: Fix nir_op_mov handling in nir_collect_src_uniforms 
For mov we need to follow the swizzle for the destination component, not
grab swizzle[0] for some random source.

Fixes: a406fff78a ("nir/inline_uniforms: support vector uniform")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Faith Ekstrand
87004fa701 nir: Rework nir_scalar_chase_movs a bit 
The cases in the if are the same as the cases we're using for the early
break.  Just check the things and break if it's not a handleable case.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24704>
 2023-08-16 21:42:30 +00:00
Rhys Perry
cf796aa885 radv: vectorize scratch access 
fossil-db (gfx1100):
Totals from 20 (0.01% of 133461) affected shaders:
Instrs: 49421 -> 49134 (-0.58%)
CodeSize: 251668 -> 249604 (-0.82%); split: -0.83%, +0.01%
Latency: 178126 -> 178412 (+0.16%); split: -0.16%, +0.32%
InvThroughput: 23565 -> 23646 (+0.34%); split: -0.05%, +0.39%
VClause: 957 -> 943 (-1.46%)
Copies: 5770 -> 5801 (+0.54%); split: -0.36%, +0.90%
PreVGPRs: 1368 -> 1359 (-0.66%)

Regressions seem to be a couple of cases of bad RA luck.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry
81641b0155 radv: vectorize RT stack access 
fossil-db (gfx1100):
Totals from 10 (0.01% of 133461) affected shaders:
MaxWaves: 176 -> 174 (-1.14%)
Instrs: 39260 -> 38710 (-1.40%)
CodeSize: 202272 -> 197288 (-2.46%)
VGPRs: 888 -> 900 (+1.35%)
Latency: 82306 -> 81762 (-0.66%); split: -0.68%, +0.02%
InvThroughput: 11182 -> 11158 (-0.21%); split: -0.52%, +0.30%
VClause: 721 -> 700 (-2.91%)
SClause: 1147 -> 1148 (+0.09%); split: -0.17%, +0.26%
Copies: 3625 -> 3891 (+7.34%)
PreVGPRs: 819 -> 845 (+3.17%); split: -0.37%, +3.54%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry
6f315e6049 nir/opt_load_store_vectorize: support scratch access 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry
afb465013f nir/lower_shader_calls: fix align_offset 
I don't think this does anything at the moment, because all accesses are
scalar aligned.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry
5a7efccdc3 radv/gfx11: re-enable 0001/1110 clear values 
Since 87444bb7ab, vi_alpha_is_on_msb always
returned false here. The new version matches radeonsi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Rhys Perry
19f73f8eb4 radv: support 128bpp comp-to-single with all colors 
Previously, it was restricted to clear colors where R==G==B, but it seems
to work if that isn't the case.

This restriction was probably a leftover from before comp-to-single.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Rhys Perry
e2c7ce3719 radv: fix 128bpp comp-to-single clears 
We were clearing GB to A, instead of R.

This fixes some red tinting in Overwatch 2 when shadow quality is set to
"Ultra".

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 7451eb1d61 ("radv: implement DCC fast clears with comp-to-single")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9446
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Rhys Perry
405f3bf990 radv: disable 64-bit color attachments 
These work in some circumstances (dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc),
but I'm not sure if they work in all, blending certainly doesn't work and
this probably wasn't intended in the first place.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 01bd012edd ("amd: fix 64-bit integer color image clears")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Feng Jiang
ad40073e4e meson: Rename dri-vdpau.dyn to dri.dyn 
File 'src/gallium/targets/dri-vdpau.dyn' is now shared by multiple
targets and not just VDPAU, so renamed it to 'dri.dyn' as suggested
by Marek Olšák.

Related link:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23177#note_2030493

Suggested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24569>
 2023-08-16 16:57:54 +00:00
Emma Anholt
f0a362d5ba turnip: Move sysmem clears to the first subpass that uses them. 
This is a partial fix for the case where
VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT and the aliased attachment clears
the attachment that was last used in a previous subpass (we have to move
the stores to the last used subpass, as well).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt
21334e3b53 turnip: Move gmem clears and loads to the first subpass that uses them. 
This will help us share gmem space between attachments that aren't used at
the same time.  It's also a correctness fix for
VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT, because they're supposed to
happen at the first subpass using the attachment, not the start of the
renderpass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt
4cfd021e3f turnip: Save the renderpass's clear values in the cmdbuf state. 
For delaying clears to subpass begin time, I needed to save these until
later.  Turns out this cleans up a good bit of threading these values all
through the command buffer setup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt
139cc91697 turnip: Skip emitting empty CP_COND_REG_EXEC. 
If we ended up emitting no code to be conditionally run, then drop the
whole conditional exec packet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt
c96b2cc511 turnip: Track the first/last subpass an attachment is used in. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Emma Anholt
fce10ddf0f vulkan/util: Make multialloc succeed with 0 allocations. 
I wanted to use it for the attachments and clear values of a
vkCmdBeginRenderPass(), but both can be 0 count.  In that case, we would
end up with vk_default_alloc(0,0) because nothing had set the alignment,
and assertion fail instead of allocating 0 bytes.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20994>
 2023-08-16 16:02:51 +00:00
Matt Turner
d142c845d0 Revert "intel/fs: only avoid SIMD32 if strictly inferior in throughput" 
This reverts commit 6b494745be.

The logic is not entirely correct: the comparison is between two
static-analysis estimates of a dynamic system with variables that aren't
captured by the shader source, so using ">" will always have greater potential
to cause regressions whenever the performance difference between the two builds
is something not captured by the static model, no matter how much the model is
improved.

Reference: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9262
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24615>
 2023-08-16 14:56:15 +00:00
Lionel Landwerlin
aebe584586 iris: ensure stalling pipe control before fast clear 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 87149cc545 ("blorp: update and move fast clear PIPE_CONTROLs to drivers")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24718>
 2023-08-16 13:59:46 +00:00
Christian Gmeiner
bd1d322107 etnaviv: fix null pointer dereference 
Fixes: 734b15186b ("etnaviv: Stop passing around nir_dest")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24717>
 2023-08-16 13:17:23 +00:00
Erik Faye-Lund
cff6c4d885 docs: upgrade bootstrap to 5.3.1 
Bootstrap 5.3.1 is out, implementing the color fix we introduced to make
dark-mode more readable. So let's update to that, and drop our override.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24670>
 2023-08-16 10:47:36 +00:00
Dor Askayo
daa1f789b5 nouveau: add exported GEM handles to the global list 
Adding GEM handles to the global list is necessary to allow
maintaining a single reference count for handles that are shared
between multiple buffer objects.

Since exported handles can end up being shared with other buffer
objects, as in the case that drmPrimeHandleToFD() and gbm_bo_import()
are called externally to Mesa, they too must be added to the global
list.

Unfortunately, doing this properly requires a new libdrm API. Use
the best possible option for now.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9552

Signed-off-by: Dor Askayo <dor.askayo@gmail.com>
Acked-by: Karol Herbst <git@karolherbst.de>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24648>
 2023-08-16 10:28:22 +00:00
Andrew Randrianasulu
d7cc19363f nv50/ir: Remove few nvc0 specific defines from nv50-specific header. 
Compile, and run-tested on nv92

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7259>
 2023-08-16 10:11:45 +00:00
Karol Herbst
7f63d2ebdb nv50: fix code uploads bigger than 0x10000 bytes 
The hardware has a max limit on how much data we can upload in one go via
the 2D engine. Just split the uploads up.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9571
Acked-by: M Henning <drawoc@darkrefraction.com>
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24706>
 2023-08-16 09:50:33 +00:00
Qiang Yu
8e13736222 radeonsi: remove unused arg of get_tcs_tes_buffer_address 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:36:37 +08:00
Qiang Yu
0e97fe38b7 radeonsi: part mode standalone tcs support aco compile 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:36:37 +08:00
Qiang Yu
59f4504d05 radeonsi: add si_aco_build_shader_part 
Now it only has tcs epilog build, will add more prolog/epilog to it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:36:37 +08:00
Qiang Yu
8631851b8f radeonsi: change si_fill_aco_options args 
Prepare to be shared with prolog/epilog generation which
does not have si_shader param.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:29 +08:00
Qiang Yu
04aadb32ad radeonsi: add si_get_tcs_epilog_args 
For shared with aco tcs epilog creation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:29 +08:00
Qiang Yu
8e0cff56f3 radeonsi: remove separate_prolog arg from prolog/epilog build 
It's always true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu
b744405aa2 radeonsi: extract si_llvm_build_shader_part 
Prepare for aco code path.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu
e797bd78c9 radeonsi: fill part mode tcs aco shader info 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu
ac867af099 radeonsi: share si_get_tcs_out_patch_stride with aco 
Move it out of llvm to be shared with aco.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu
1001478a68 radeonsi: support upload multi part shader binary 
Need to split shader binary into exec and data part, then combine
exec and data of all shader parts separately. So const data symbols
in code need to be relocated.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu
85c0f31099 radeonsi: add exec_size to shader binary 
Used by aco binary to split exec code and const data when combine
multi part shader binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
 2023-08-16 11:25:28 +08:00
Qiang Yu
51a8479a51 aco: use semantic location as io temp index 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu
4c7fdebf9b ac/nir/tess: move tess factor output out of control flow 
For radeonsi aco compile which can't handle outputs without
nir_lower_io_to_temporaries().

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu
4756388038 aco,radeonsi: save const addr to symbol 
For radeonsi to relocation const data when combine multiple
shader parts to a single one. So the final shader binary will
begin with exec code of all parts then const data.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu
facbd13df1 aco: skip scratch init when no scratch arg provide 
epilog does not use scratch so has no scratch arg.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00
Qiang Yu
d3333609e6 aco: don't emit s_endpgm for tcs with epilog 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
 2023-08-16 02:27:45 +00:00