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1516 Commits

Author SHA1 Message Date
Samuel Pitoiset 395dee0d89 radv: drop si_ prefix from all functions 
Most of these functions were copied from RadeonSI but they should be
prefixed with radv_ instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26854>
 2024-01-04 08:40:37 +00:00
Samuel Pitoiset 89947eb151 radv: remove radv_write_scissors() 
This function is useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26854>
 2024-01-04 08:40:36 +00:00
Samuel Pitoiset aa1eb54b3b radv: constify a variable in radv_emit_depth_control() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26847>
 2024-01-04 07:54:41 +00:00
Samuel Pitoiset 8b7b5be98b radv: disable stencil test without a stencil attachment 
Implementations are supposed to do that per the Vulkan spec.

This fixes the following new VKCTS tests
dEQP-VK.pipeline.*.stencil.no_stencil_att.*

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26847>
 2024-01-04 07:54:40 +00:00
Samuel Pitoiset 7ea48145a1 radv: stop clearing CMASK to 0xcc when FMASK is present on GFX9 
This is incorrect because clearing CMASK to 0xCC should only happen
for fast clears with DCC and FMASK/CMASK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26634>
 2024-01-03 13:58:06 +00:00
Samuel Pitoiset db9816fd66 radv: add support for NULL index buffer 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26757>
 2024-01-03 11:24:27 +00:00
Samuel Pitoiset 744cb98bc6 radv: add support for version 2 of all descriptor binding commands 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26757>
 2024-01-03 11:24:27 +00:00
Samuel Pitoiset 5f63624701 radv: rename RADV_GRAPHICS_STAGES to RADV_GRAPHICS_STAGE_BITS 
For consistency with RADV_RT_STAGE_BITS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26757>
 2024-01-03 11:24:27 +00:00
Samuel Pitoiset 0481723cf0 radv: move radv_depth_clamp_mode to radv_cmd_buffer.c 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26713>
 2023-12-19 09:48:35 +00:00
Samuel Pitoiset 4353b0ad72 radv: move emitting the fb mip tail workaround when rendering begins 
It doesn't have to be emitted in the draw path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
 2023-12-18 13:06:29 +00:00
Samuel Pitoiset 7dd7e551b1 radv: stop checking FMASK for the fb mip tail workaround 
Vulkan doesn't allow mipmaps with MSAA images, so checking for FMASK
shouldn't have any effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
 2023-12-18 13:06:29 +00:00
Samuel Pitoiset 57efe44f43 radv: add missing HTILE support for fb mip tail workaround 
PAL also applies to depth/stencil images with HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26589>
 2023-12-18 13:06:29 +00:00
Samuel Pitoiset 1ef5feac5e radv: fix binding partial depth/stencil views with dynamic rendering 
With dynamic rendering, it's allowed to begin rendering with depth or
stencil only but still with a depth/stencil format. The test below
checks that unbound part of ds isn't modified, if depth is bound and
stencil not and vice versa.

This fixes a recent CTS
dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25350>
 2023-12-14 12:54:23 +00:00
Samuel Pitoiset 98ea540158 radv: add support for MRT compaction with PS epilogs 
Now that PS epilogs are always compiled during cmdbuf recording, we
have all information to enable MRT compaction, for optimal performance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26667>
 2023-12-14 09:51:26 +01:00
Samuel Pitoiset 78e45221bd radv: emit the task shader in radv_emit_graphics_pipeline() 
It's a better place to do so.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26414>
 2023-12-14 07:57:32 +00:00
Samuel Pitoiset 0605631094 radv: stop clearing FMASK_COMPRESS_1FRAG_ONLY for TC-compat CMASK images 
TC-compat CMASK means Fmask decompression isn't needed because the hw
can read it directly from shaders, so this shouldn't have any effects.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26575>
 2023-12-13 07:48:51 +00:00
Samuel Pitoiset c70c269b16 radv: remove useless check for TC-compat CMASK images during fb emission 
The FMASK decompression only happens for images with FMASK and without
TC-compat CMASK, so both can never be TRUE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26575>
 2023-12-13 07:48:51 +00:00
Timur Kristóf a632024700 radv: Implement vkCmdWriteBufferMarker2AMD on transfer queues. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
 2023-12-09 01:49:13 +00:00
Timur Kristóf 23590a4e98 radv: Implement barriers for transfer queues. 
The current flush flags in RADV don't really match the SDMA HW,
so just always emit a NOP packet, for now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
 2023-12-09 01:49:13 +00:00
Timur Kristóf 1c8c3e5a7a radv: Don't retile DCC on transfer queues. 
Instead, the retile will be executed on another queue type
when the image is transitioned to another queue.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25834>
 2023-12-08 14:46:17 +00:00
Juston Li dc7c1d989b radv: enable stippledBresenhamLines on GFX9 chips 
This isn't supposed to work nor does it match radeonsi but setting
AUTO_RESET_CNTL=0 by default for GFX9 chips is what gets it passing
linestrip CTS tests:

dEQP-VK.rasterization.primitives.dynamic_stipple.bresenham_line_strip
dEQP-VK.rasterization.primitives.dynamic_stipple_and_topology.bresenham_line_strip
dEQP-VK.rasterization.primitives.dynamic_stipple_and_topology.bresenham_line_strip_wide
dEQP-VK.rasterization.primitives.static_stipple.bresenham_line_strip

Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24623>
 2023-12-07 19:10:15 +00:00
Samuel Pitoiset 79cf2b6824 radv: determine and emit SPI_SHADER_Z_FORMAT for PS epilogs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Samuel Pitoiset 8b87c985b0 radv: prepare the PS epilog key for exporting MRTZ on RDNA3 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
 2023-12-06 11:49:31 +00:00
Samuel Pitoiset a3b3a7d36a radv: remove unused code for compiling PS epilogs as part of pipelines 
Since we switched to the "on-demand" path for GPL, this is dead code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
 2023-12-06 08:01:46 +00:00
Samuel Pitoiset e88973fd02 radv: change the reset stipple pattern mode for adjacent lines 
Ported from RadeonSI. This isn't covered by VK CTS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
 2023-12-05 18:29:29 +00:00
Samuel Pitoiset 16d5ffc3ee radv: update the reset stipple pattern mode 
PAL recently changed the mode. This doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26429>
 2023-12-05 18:29:29 +00:00
Samuel Pitoiset 338319741c radv: add DGC support for mesh shader only 
This only implements mesh shaders with DGC because task shaders are
really tricky. I will address them later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
 2023-12-05 14:17:39 +00:00
Samuel Pitoiset 400cfa0eba radv: remove never used binds_state for DGC 
This has been removed a while ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25890>
 2023-12-05 14:17:39 +00:00
Eric Engestrom 778000ec7f radv: update symbols that have become aliases for newer ones 
All of these have been renamed in the spec (usually by being promoted);
renamed them in our code too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26490>
 2023-12-04 10:45:48 +00:00
Samuel Pitoiset ced313eec8 radv: make sure to prefetch the compute shader for DGC 
It was never prefetched. These two helpers should be refactored with
radv_dispatch() though.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
 2023-12-01 12:25:46 +00:00
Samuel Pitoiset ab6cf1592f radv: fix bogus interaction between DGC and RT with descriptor bindings 
pipeline_is_dirty was never TRUE because it's emitted in the before
helper. This might fix bad interactions between DGC and RT because
they both use compute shaders and descriptor bindings need to be
re-emitted.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
 2023-12-01 12:25:46 +00:00
Bas Nieuwenhuizen 6ff98f9313 radv: Add implementation of cmd buffers for a sparse binding queue. 
None of the commands are allowed on these ...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16935>
 2023-11-29 17:37:37 +00:00
Samuel Pitoiset 6c7265338d radv: add support for task shader invocations queries on GFX10.3 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset 623b7033c5 radv: make some gang functions non-static 
They will be used to create a gang CS when beginning a query if not
already present.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset b7d668a819 radv: add support for mesh shader invocations queries on GFX10.3 
Also emulated with a GDS atomic counter in shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950>
 2023-11-21 15:24:49 +00:00
Samuel Pitoiset ec82b42944 radv: add a missing async compute workaround for Tonga/Iceland 
After digging into PAL code again, I figured that Tonga/Iceland are
both affected by a hw bug related to async compute dispatches.

The solution is to change the "threadgroup" dimension mode to the
"thread" dimension mode unconditionally.

This should fix a bunch of issues related to RADV_DEBUG=nocompute on
these GPUs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7551
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6334
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4679
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26207>
 2023-11-16 11:37:43 +00:00
Tatsuyuki Ishi 538ca7801a radv: Use shader part caching helpers for VS prolog and PS/TCS epilog. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26028>
 2023-11-14 13:45:22 +00:00
Samuel Pitoiset dfc125d423 radv: fix VRS subpass attachment when HTILE can't be enabled on GFX10.3 
On GFX10.3, VRS rates need to be copied to the HTILE buffer but in some
situations, like for mips, it's not always possible to enable HTILE.
In this case, we can fallback to our internal HTILE buffer and tweak
the depth/stencil registers to use this HTILE buffer.

This fixes a bunch of VRS crashes on GFX10.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26025>
 2023-11-14 09:02:46 +00:00
Rhys Perry fd80140723 radv: set prolog as_ls if has_ls_vgpr_init_bug=true 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26111>
 2023-11-13 12:09:55 +00:00
Tatsuyuki Ishi ad4b82e192 radv: Pre-mask misaligned_mask for VS prolog. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
 2023-11-13 11:47:42 +00:00
Tatsuyuki Ishi 55d21f2f12 radv, aco: Inline struct aco_vs_input_state. 
Now that we no longer use the radv_vs_input_state pointer, we can simply
inline all the state-related fields.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
 2023-11-13 11:47:42 +00:00
Tatsuyuki Ishi 3fc3a94bce radv, aco: Rework VS prolog key handling. 
The main change is to use struct radv_vs_prolog_key directly instead of
the compressed representation to simplify an upcoming rework in prolog /
epilog caching. In doing so the state struct pointer was replaced with
an inline struct.

Care was also taken to pre-mask all the states with the active attribute
mask and other masks when it makes sense; this ensures that we don't
accidentally use information not hashed into the key during compilation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
 2023-11-13 11:47:42 +00:00
Tatsuyuki Ishi 5cc7f54f15 radv: Remove last VS prolog reuse logic. 
This was broken as the field was never assigned to. This will also be
dropped from the upcoming prolog/epilog lookup rework, as it adds to
code complexity while the benefit of saving one hash table memory access
seems questionable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
 2023-11-13 11:47:41 +00:00
Samuel Pitoiset 55e48d7e0f radv: enable DGC preprocessing when all push constants are inlined 
It's not possible when they aren't all inlined because they need to be
copied to the upload BO and the DGC shader also copies the ones that
come from the indirect layout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25935>
 2023-11-13 08:28:53 +00:00
Samuel Pitoiset 0112a245f5 radv: add a helper to determine if it's possible to preprocess DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25935>
 2023-11-13 08:28:53 +00:00
Timur Kristóf ec0605ff72 radv: Add temporary BO for transfer queues. 
Some copy operations are poorly supported by the SDMA hardware,
meaning that the built-in packets don't support them, so we will
need to work around that by copying to and from a temporary BO.

The size of the temporary buffer was chosen so that it can fit
at least one full pixel row of the largest possible image.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25831>
 2023-11-01 13:21:01 +00:00
Samuel Pitoiset e4a1bc70dd radv: bind the non-dynamic graphics state from the pipeline unconditionally 
The following sequence is valid (although weird) but many other drivers
(including RADV) were broken:
    - bind pipeline with some static state
    - set state command for that static state (to a bad value)
    - bind the same pipeline again
    - draw

Fixes new dEQP-VK.dynamic_state.*.double_static_bind.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25954>
 2023-11-01 09:44:13 +00:00
Bas Nieuwenhuizen c4fb827441 radv: Add compute DGC preprocessing support. 
This should reduce the overhead due to reduced syncs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25835>
 2023-11-01 00:06:10 +00:00
Bas Nieuwenhuizen 108227a84e radv: Add DGC preprocessing barrier support. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25835>
 2023-11-01 00:06:09 +00:00
Samuel Pitoiset 5176f75e0d radv: remove unnecessary VS_PARTIAL_FLUSH for NGG streamout 
This used to be a PS_PARTIAL_FLUSH to fix synchronization issues with
NGG streamout on RDNA2 but it's no longer needed for RDNA3. It's
already synchronized in CmdEndTransformFeedbackEXT().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25903>
 2023-10-30 08:51:51 +00:00