This should fix such valgrind warnings:
==37417== Uninitialised byte(s) found during client check request
==37417== at 0x6183471: blob_write_bytes (blob.c:163)
==37417== by 0x629785B: encode_type_to_blob (glsl_types.cpp:2760)
==37417== by 0x61E68D8: write_variable (nir_serialize.c:293)
==37417== by 0x61E6F6A: write_var_list (nir_serialize.c:421)
==37417== by 0x61EBA7A: nir_serialize (nir_serialize.c:2018)
==37417== by 0x5B5E007: serialize_nir_part (brw_program_binary.c:135)
==37417== by 0x5B5E7F3: brw_serialize_program_binary (brw_program_binary.c:299)
==37417== by 0x5FEF5FF: write_program_payload (program_binary.c:177)
==37417== by 0x5FEF7BB: _mesa_get_program_binary_length (program_binary.c:225)
==37417== by 0x5E3D31D: get_programiv (shaderapi.c:912)
==37417== by 0x5E3F730: _mesa_GetProgramiv (shaderapi.c:1827)
==37417== by 0x111DA0: program_binary_save_restore (shader_runner.c:686)
==37417== Address 0x8f59481 is 81 bytes inside a block of size 480 alloc'd
==37417== at 0x483B7F3: malloc (vg_replace_malloc.c:309)
==37417== by 0x618CE67: ralloc_size (ralloc.c:123)
==37417== by 0x618CF35: rzalloc_size (ralloc.c:155)
==37417== by 0x618D245: rzalloc_array_size (ralloc.c:234)
==37417== by 0x629041D: glsl_type::glsl_type(glsl_struct_field const*, unsigned int, glsl_interface_packing, bool, char const*) (glsl_types.cpp:148)
==37417== by 0x6293EC3: glsl_type::get_interface_instance(glsl_struct_field const*, unsigned int, glsl_interface_packing, bool, char const*) (glsl_types.cpp:1271)
==37417== by 0x604C878: (anonymous namespace)::per_vertex_accumulator::construct_interface_instance() const (builtin_variables.cpp:365)
==37417== by 0x6050722: (anonymous namespace)::builtin_variable_generator::generate_varyings() (builtin_variables.cpp:1568)
==37417== by 0x60509CA: _mesa_glsl_initialize_variables(exec_list*, _mesa_glsl_parse_state*) (builtin_variables.cpp:1600)
==37417== by 0x6149AE9: _mesa_ast_to_hir(exec_list*, _mesa_glsl_parse_state*) (ast_to_hir.cpp:131)
==37417== by 0x60706D6: _mesa_glsl_compile_shader (glsl_parser_extras.cpp:2222)
==37417== by 0x5E3DC16: _mesa_compile_shader (shaderapi.c:1211)
==37417== Use of uninitialised value of size 8
==37417== at 0x529AE13: ??? (in /usr/lib/x86_64-linux-gnu/libz.so.1.2.11)
==37417== by 0x6184075: util_hash_crc32 (crc32.c:127)
==37417== by 0x5FEF401: write_program_binary (program_binary.c:95)
==37417== by 0x5FEF8BC: _mesa_get_program_binary (program_binary.c:252)
==37417== by 0x5E40E22: _mesa_GetProgramBinary (shaderapi.c:2411)
==37417== by 0x4914057: stub_glGetProgramBinary (piglit-dispatch-gen.c:24737)
==37417== by 0x111E4A: program_binary_save_restore (shader_runner.c:704)
==37417== by 0x11F765: piglit_display (shader_runner.c:5112)
==37417== by 0x499082F: run_test (piglit_fbo_framework.c:52)
==37417== by 0x4980E89: piglit_gl_test_run (piglit-framework-gl.c:229)
==37417== by 0x110DA9: main (shader_runner.c:72)
v2: - decode_glsl_struct_field_from_blob and
encode_glsl_struct_field should be `static`
( Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> )
v3: - we can get rid of `struct packed_struct_field_flags`
( Tapani Pälli <tapani.palli@intel.com> )
- we can get rid of `unsigned __pad: 15` bitfield
( Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> )
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5054>
We initially used this debug option to mean "don't bother registering
the OA configuration into the kernel".
This change makes this option suppress any interaction with the
i915/perf interface. This is useful when debugging self modifying
batches with performance queries while running on the intel_mi_runner.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
This has the same kernel requirements are VK_INTEL_performance_query
v2: Fix empty queue submit (Lionel)
v3: Fix autotool build issue (Piotr Byszewski)
v4: Fix Reset & Begin/End in same command buffer, using soft-pin &
relocation on the same buffer won't work currently. This version
uses a somewhat dirty trick in anv_execbuf_add_bo (Piotr Byszewski)
v5: Fix enumeration with null pointers for either pCounters or
pCounterDescriptions (Piotr)
Fix return condition on enumeration (Lionel)
Set counter uuid using sha1 hashes (Lionel)
v6: Fix counters scope, should be COMMAND_KHR not COMMAND_BUFFER_KHR (Lionel)
v7: Rebase (Lionel)
v8: Rework checking for loaded queries (Lionel)
v9: Use new i915-perf interface
v10: Use anv_multialloc (Jason)
v11: Implement perf query passes using self modifying batches (Lionel)
Limit support to softpin/gen8
v12: Remove spurious changes (Jason)
v13: Drop relocs (Jason)
v14: Avoid overwritting .sType in
VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Lionel)
v15: Don't copy the entire
VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Jason)
Reuse anv_batch rather than custom packing (Jason)
v16: Fix missing MI_BB_END in reconfiguration batch
Only report the extension with kernel support (perf_version >= 3)
v17: Some cleanup of unused stuff
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
For a future extension we want to be able to list the counters. Our
existing sets counters might contain the same counters multiple times.
This is a side effect of the fixed OA counters in the HW. We track
thoses with a mask so that we know when a counter is available from
multiple metrics.
v2: Use BITFIELD64_BIT() (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
This change adds a call/return execution mode for secondary command
buffer rather than the existing copy into the primary batch mode.
v2: Rework convention to avoid burning an ALU register (Jason)
v3: Use anv_address_add() (Jason)
v4: Move command emissions to anv_batch_chain.c (Jason)
v5: Also move last MI_BBS emission in secondary command buffer to
anv_batch_chain.c (Jason)
v6: Fix end secondary command buffer end (Jason)
v7: Refactor anv_batch_address() to remove additional emit functions
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
This instruction has a group with the same name than another field above :
<field name="Data DWord" start="64" end="95" type="uint"/>
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
The script was replacing the offset of the field first with the second
one in the group.
This change ignore anything a group within an instruction.
v2: Drop unused variable (Rafael)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
We can just set the extent and not bufferRowLength/bufferImageHeight,
and the extent may not be a multiple of the block size if it covers the
entire image. In this case we have to first divide to get the
width/height in terms of blocks, and then multiply by the block size to
get the buffer's pitch and layer size. Multiplying and dividing instead
won't get the correct result when the extent covers the entire image and
isn't a multiple of the block size. This also makes the code easier to
follow because we don't calculate a pitch in non-sensical units (bytes
times the block width) as an intermediate step.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
Previously we only supported BLIT_SRC_BIT and BLIT_DEST_BIT together, so
we didn't have to worry about initializing blit-related fields for
texture-only formats, but it turns out that 2d blits work out just fine
with these formats and we'll need to enable BLIT_SRC_BIT for
texture-only formats due to a Vulkan requirement on compressed formats.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5098>
All it takes are a couple small tweaks to the clone infrastructure to
allow us to use it without any remap table at all. This reduces code
duplication and the chances for bugs that come with it. In particular,
the hand-rolled nir_alu_instr_clone didn't preserve no_[un]signed_wrap,
or source/destination modifiers.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5094>
It sure looks like it should be a Boolean value, but it's not. The
values that we really want for later platforms are either 2 or 3. The
old intel_stub.c in shader-db just always returns 3
(I915_GEM_PPGTT_FULL). This returns the same set of values per platform
that kernel 5.6.13 would.
When using the shim for ICL with i965 driver, this fixes:
i965 requires softpin (Kernel 4.5) on Gen10+.
Fixes: 0f4f1d70bf ("intel: add stub_gpu tool")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5061>
Andrii Simiklit