Commit Graph

56219 Commits

Author SHA1 Message Date
Juha-Pekka Heikkila 2dfbbeca50 i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6
This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD,
saving one instruction and two temporary registers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-16 22:46:45 -07:00
Juha-Pekka Heikkila 0974706671 i965/vec4: Add support for the MAC instruction.
This allows us to generate the MAC (multiply-accumulate) instruction,
which can be used to implement some expressions in fewer instructions
than doing a series of MUL and ADDs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-16 22:46:45 -07:00
Juha-Pekka Heikkila 306ed81b93 i965: Add writes_accumulator flag
Our hardware has an "accumulator" register, which can be used to store
intermediate results across multiple instructions.  Many instructions
can implicitly write a value to the accumulator in addition to their
normal destination register.  This is enabled by the "AccWrEn" flag.

This patch introduces a new flag, inst->writes_accumulator, which
allows us to express the AccWrEn notion in the IR.  It also creates a
n ALU2_ACC macro to easily define emitters for instructions that
implicitly write the accumulator.

Previously, we only supported implicit accumulator writes from the
ADDC, SUBB, and MACH instructions.  We always enabled them on those
instructions, and left them disabled for other instructions.

To take advantage of the MAC (multiply-accumulate) instruction, we
need to be able to set AccWrEn on other types of instructions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-16 22:46:45 -07:00
Juha-Pekka Heikkila 30c35d1dcb i965: Add is_accumulator() function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-04-16 22:46:45 -07:00
Matt Turner 6541f1b4d0 i965: Add reads_accumulator_implicitly() function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-16 22:46:44 -07:00
Anuj Phogat cb6566f9df mesa: Add error condition for integer formats in glGetTexImage()
OpenGL 4.0 spec, page 306 suggests an INVALID_OPERATION in glGetTexImage
if :
   "format is one of the integer formats in table 3.3 and the internal
    format of the texture image is not integer, or format is not one of
    the integer formats in table 3.3 and the internal format is integer."

V2: Use helper function _mesa_is_format_integer()

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-04-16 18:37:06 -07:00
Anuj Phogat 3135668254 mesa: Add helper function _mesa_is_format_integer()
This function will be used in the following patch.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-04-16 18:37:06 -07:00
Anuj Phogat fdd8bebc22 mesa: Fix glGetVertexAttribi(GL_VERTEX_ATTRIB_ARRAY_SIZE)
mesa currently returns 4 when GL_VERTEX_ATTRIB_ARRAY_SIZE is queried
for a vertex array initially set up with size=GL_BGRA. This patch
makes changes to return size=GL_BGRA as required by the spec.

Fixes Khronos OpenGL CTS test: vertex_array_bgra_basic.test

V2: Use array->Format instead of adding a new variable

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
2014-04-16 18:37:06 -07:00
Anuj Phogat 80b4a36fed glsl: Fix copy-paste error in linker_warning()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-16 18:37:06 -07:00
Michel Dänzer 7286739b9b r600g: Disable LLVM by default at runtime for graphics
For graphics, the LLVM compiler backend currently has many shortcomings
compared to the non-LLVM one. E.g. it can't handle geometry shaders yet,
but that's just the tip of the iceberg.

So building Mesa with --enable-r600-llvm-compiler is currently not
recommended for anyone who doesn't want to work on fixing those issues.
However, for protection of users who end up enabling it anyway for some
reason, let's disable the LLVM backend at runtime by default. It can be
enabled with the environment variable R600_DEBUG=llvm.

Cc: "10.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-17 10:15:59 +09:00
Roland Scheidegger f23d1160c2 gallivm: fix compilation with llvm 3.5 r206241+
Just adjust to the ever-changing API, pass in MCContext when creating the
MCDisassembler.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-16 19:57:47 +02:00
Marek Olšák 11459436d9 r600g,radeonsi: share some of gfx flush code
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:52 +02:00
Marek Olšák adfadeadd8 r600g,radeonsi: share r600_flush_from_st
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:52 +02:00
Marek Olšák 586011486d r600g: merge r600_flush with r600_context_flush
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák d4edc60767 radeonsi: merge si_flush with si_context_flush
This also removes si_flush_gfx_ring.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák 70cf6639c3 gallium/radeon: create and return a fence in the flush function
All flush functions get a fence parameter. cs_create_fence is removed.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák 3e9d2cbca2 r600g: remove redundant r600_flush_dma_from_winsys
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák dd72c327e9 winsys/radeon: fold cs_set_flush_callback into cs_create
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák c6033a6cb8 radeonsi: cleanup redundant computation of flush flags and rename a function
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák fc151b08be r600g: remove redundant r600_flush_from_winsys
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák b2238b3452 winsys/radeon: remove cs_write_reloc, add simpler cs_get_reloc
The only difference is that it doesn't write to the CS and only returns
the index.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
Marek Olšák 927213f33d winsys/radeon: consolidate hash table lookup
I should have done this long ago.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-04-16 14:02:51 +02:00
José Fonseca f81305c0cb util/u_debug: Add noreturn attribute to _debug_assert_fail().
As recommended by
http://clang-analyzer.llvm.org/annotations.html#attr_noreturn

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-04-16 11:44:17 +01:00
Iago Toral Quiroga 6d0e30c6a3 glsl: Properly handle blocks that define the same field name.
Currently we can have name space collisions between blocks that define the same
fields. For example:

in block
{
    vec4 Color;
} In[];

out block
{
    vec4 Color;
} Out;

These two blocks will assign the same interface name (block.Color) to the Color
field in flatten_named_interface_blocks_declarations.cpp, leading to havoc.
This was breaking badly the gl-320-primitive-shading test from ogl-samples.

The patch uses the block instance name to avoid collisions, producing names
like block.In.Color and block.Out.Color to avoid the name clash.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76394
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 22:18:43 -07:00
Michel Dänzer 6ac5a5e383 r600g/radeonsi: Map transfer staging texture unsynchronized when possible
The transfer staging texture is always freshly allocated, so for write-only
transfers we don't need to explicitly wait for the BO to become idle.

Squeezes a few hundered MB/s more out of x11perf -shmput500 with glamor.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-16 12:11:27 +09:00
Matt Turner 9fed627234 Revert "i965/fs: Only sweep NOPs if register coalescing made progress."
This reverts commit f092e8951c.

Didn't mean to push this...
2014-04-15 17:27:55 -07:00
Matt Turner f092e8951c i965/fs: Only sweep NOPs if register coalescing made progress.
Otherwise there's nothing to do.
2014-04-15 16:28:04 -07:00
Eric Anholt 7ae870211d i965: Fix buffer overruns in MSAA MCS buffer clearing.
This manifested as rendering failures or sometimes GPU hangs in
compositors when they accidentally got MSAA visuals due to a bug in the X
Server.  Today we decided that the problem in compositors was equivalent
to a corruption bug we'd noticed recently in resizing MSAA-visual
glxgears, and debugging got a lot easier.

When we allocate our MCS MT, libdrm takes the size we request, aligns it
to Y tile size (blowing it up from 300x300=900000 bytes to 384*320=122880
bytes, 30 pages), then puts it into a power-of-two-sized BO (131072 bytes,
32 pages).  Because it's Y tiled, we attach a 384-byte-stride fence to it.
When we memset by the BO size in Mesa, between bytes 122880 and 131072 the
data gets stored to the first 20 or so scanlines of each of the 3 tiled
pages in that row, even though only 2 of those pages were allocated by
libdrm.  In the glxgears case, the missing 3rd page happened to
consistently be the static VBO that got mapped right after the first MCS
allocation, so corruption only appeared once window resize made us throw
out the old MCS and then allocate the same BO to back the new MCS.

Instead, just memset the amount of data we actually asked libdrm to
allocate for, which will be smaller (more efficient) and not overrun.
Thanks go to Kenneth for doing most of the hard debugging to eliminate a
lot of the search space for the bug.

Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77207
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 14:34:47 -07:00
Eric Anholt e5b86cb64b meta: Add support for MSAA resolves from 2D_MS_ARRAY textures.
We don't have any piglit tests for this currently.

v2: Use vec3s for the texcoords so it has some hope of working.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 14:34:45 -07:00
Eric Anholt 234db60954 meta: Add an accelerated glCopyTexSubImage using glBlitFramebuffer.
You'll note from the previous commits that there's something of a loop
here: You call CTSI, which calls BlitFB, then if things go wrong that
falls back to CTSI.  As a result, meta CTSI reaches over into blitfb to
tell it "no, don't try that fallback".

v2: Drop the _mesa_update_state(), which was only necessary due to use of
    _mesa_clip_blit() in _mesa_meta_BlitFramebuffer() in another patch
    series.
v3: Drop an _EXT suffix I copy-and-pasted.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 14:34:22 -07:00
Eric Anholt 70961c032f meta: Add support for CUBE_MAP_ARRAY to generatemipmap.
I added support to bind_fbo_image in the process of building meta
CopyTexSubImage, and found that it broke generatemipmap because previously
we would just throw a GL error there and then end up with an incomplete
FBO and fallback.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 14:34:22 -07:00
Eric Anholt bb3f983d10 meta: Infer bind_fbo_image parameters from an incoming image.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 14:34:22 -07:00
Eric Anholt cd808ac848 meta: Move bind_fbo_image() code back to meta.c, to reuse it elsewhere.
I need to do the same code again for CopyTexSubImage().

v2: Drop incorrect, not-terribly-useful comment (review by Ken)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 14:34:22 -07:00
Eric Anholt 4cc42805e7 meta: Refactor the BlitFramebuffer depth CopyTexImage fallback.
This avoids a ReadPixels() if there's accelerated CopyTexImage present.
It now requires GLSL as opposed to just fragment programs, but we don't
have any drivers that do ARB_fp but not GLSL.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 14:34:22 -07:00
Eric Anholt b702233f53 meta: Refactor the BlitFramebuffer color CopyTexImage fallback.
There shouldn't be anything special about copying out a subset of the src
rb to a temp before texturing from it, so just do it when we're figuring
out our src texture binding.

This drops Anuj's change to copy an extra border of 1 pixel around the src
area.  I can't see how that change could be valid, and presumably if
there's some filtering problem at edges we just need to set the right
wrap mode.

v2: Don't fall back to swrast on non-2D/RECT/2D_MS textures when we can
    still CopyTexSubImage.  Fixes a segfault regression on i965 with
    gl-3.2-layered-rendering-blit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-04-15 14:34:06 -07:00
Eric Anholt 4e43299633 meta: Drop blit src size fallback.
I think we can assert that renderbuffer size is <= maximum 2D texture
size.  Our source coordinates should have already been clipped to the src
renderbuffer size, but haven't actually (so we could potentially have
trouble if there's scaling, and we're in the CopyTexImage path that tries
to use src size).  However, this texture size dependency was blocking the
next refactors, so I'm not sure if we want to go ahead with this series
before we get the clipping sorted out or not.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 12:27:37 -07:00
Mike Stroyan 602510395a i965: Avoid dependency hints on math opcodes
Putting NoDDClr and NoDDChk dependency control on instruction
sequences that include math opcodes can cause corruption of channels.
Treat math opcodes like send opcodes and suppress dependency hinting.

Signed-off-by: Mike Stroyan <mike@LunarG.com>
Tested-by: Tony Bertapelli <anthony.p.bertapelli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-04-15 10:31:46 -07:00
Matt Turner ad48a9a319 i965: Expand INTEL_DEBUG to uint64_t.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 10:29:00 -07:00
Matt Turner 58db339599 dri: Expand driParseDebugString return value to uint64_t.
Users will downcast if they don't have >32 debug flags.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-15 10:28:57 -07:00
Matt Turner 73400d8f70 i965/fs: Remove dead_code_eliminate_local().
Subsumed by the new dead_code_eliminate() function. No shader-db
changes.

Reviewed-by: Eric Anholt <eric@anholt.net>
2014-04-15 09:25:47 -07:00
Matt Turner 18d12336b9 i965/fs: Clear variable from live-set if it's completely overwritten.
One program affected:

instructions in affected programs:     246 -> 244 (-0.81%)

Reviewed-by: Eric Anholt <eric@anholt.net>
2014-04-15 09:25:44 -07:00
Matt Turner f34f39330b i965/fs: Reimplement dead_code_elimination().
total instructions in shared programs: 1653399 -> 1651790 (-0.10%)
instructions in affected programs:     92157 -> 90548 (-1.75%)
GAINED:                                2
LOST:                                  2

Also significantly reduces the number of optimization loop iterations:

total loop iterations in shared programs: 39724 -> 31651 (-20.32%)
loop iterations in affected programs:     21617 -> 13544 (-37.35%)

Including some great pathological cases, like 29 -> 3 in Strike Suit
Zero and 24 -> 3 in Dota2.

Reviewed-by: Eric Anholt <eric@anholt.net>
2014-04-15 09:25:11 -07:00
Matt Turner 596737ee91 i965/vec4: Let DCE eliminate dead writes in other basic blocks.
We previously stopped searching for unread writes after encountering
control flow, but we can instead just search backwards until we hit
control flow.

instructions in affected programs:     22854 -> 22194 (-2.89%)
2014-04-15 09:24:09 -07:00
Matt Turner 4dcfb92417 i965/gs: Add dummy source to prepare_channel_masks instruction.
The generator uses its destination as a source implicitly, which breaks
some assumptions in dead code elimination. Giving the instruction a
source allows us to reason about it better.
2014-04-15 09:24:09 -07:00
Matt Turner d877c643be glsl: Use M_PI_* macros.
Notice our multiple values for M_PI_2, which rounded ...32 up to
...4 and ...5.
2014-04-15 09:24:09 -07:00
Kenneth Graunke 4f20b7d3dd i965: Disable Z16 in all APIs.
We originally thought that GL 3.0 required GL_DEPTH_COMPONENT16 to map
exactly to Z16.  However, we misread the specification, thanks in part
to LaTeX reordering the tables in the PDF.

Page 180 of the GL 3.0 specification (glspec30.20080923.pdf) says:
"[...] memory allocation per texture component is assigned by the GL to
match the allocations listed in tables 3.16-3.18 as closely as possible.
[...]

Required Texture Formats
[...]
In addition, implementations are required to support the following sized
internal formats.  Requesting one of these internal formats for any
texture type will allocate exactly the internal component sizes and
types shown for that format in tables 3.16-3.17:"

Notably, however, GL_DEPTH_COMPONENT16 does /not/ appear in table 3.16
or table 3.17.  It appears in table 3.18, where the "exact" rule doesn't
apply, and it falls back to the "closely as possible" rule.

The confusing part is that the ordering of the tables in the PDF is:

Table 3.16 (pages 182-184)
Table 3.18 (bottom of page 184 to top of 185)
Table 3.17 (page 185)

Presumably, people saw table 3.16, then saw the table immediately
following with DEPTH_COMPONENT* formats, and assumed it was 3.17.

Based on a patch by Chia-I Wu, but without the driconf option to force
Z16 to be used.  It's not required, and there's apparently no benefit
to actually using it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chia-I Wu <olv@lunarg.com>
2014-04-15 02:15:11 -07:00
Kenneth Graunke be000b4d19 i965: Update comments about Z16 being slow.
We've learned a few things since we originally disabled Z16; this attempts
to summarize the issue.  I am no expert on this subject, though, so the
comment may not be totally accurate.

I did some benchmarking on GM45 and Ironlake, and discovered that for
GLBenchmark 2.7 EgyptHD, using Z16 was 3% slower on GM45 (n=15), and
4.5% slower on Ironlake (n=95).  So, we can drop the "on Ivybridge"
aspect of the comment - it's always slower.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chia-I Wu <olv@lunarg.com>
2014-04-15 02:15:11 -07:00
Michel Dänzer 313104e8d5 r600g/radeonsi: Use caching buffer manager for textures as well
Significantly reduces BO allocation / destruction overhead for transfers,
e.g. measurable via x11perf -shm{ge,pu}t* with glamor.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-15 11:34:56 +09:00
Jordan Justen 24c773fb06 i965/gen8: add debug code to show FS disasm with jump locations
Copied from similar code in gen8_vec4_generator.cpp.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-04-14 10:32:42 -07:00
Chia-I Wu 73a4761058 ilo: remove GPE state size estimation
Use size defines from genhw.
2014-04-14 20:45:04 +08:00