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Author SHA1 Message Date
Marek Olšák 2d64e8d333 radeonsi: use the correct cs for SQTT barriers for gfx9 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 862a5f7abe radeonsi: add gfx10+ support into si_cp_acquire_mem 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák a42d9db1b6 radeonsi: add si_cp_acquire_mem helper and clean up its usage for gfx6-9 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 1d5ffb13d6 radeonsi: add ACQUIRE_MEM, RELEASE_MEM PWS packet helpers 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 9690481535 radeonsi: remove SI_CONTEXT_VGT_STREAMOUT_SYNC, emit it directly 
It has only 1 use.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 1a1138817c radeonsi: add a new PM4 helper radeon_event_write 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 434eddd422 radeonsi: tweak si_test_dma_perf for better experience 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 05353cfd4f radeonsi: use better OREO_MODE programming 
We have been told to do this instead.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 0c734722a1 radeonsi/gfx11: disable RB+ when blending 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák 3de719045a radeonsi/gfx12: disallow DCC for protected content 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
Marek Olšák c90d4e0d57 radeonsi/gfx12: remove CP DMA workarounds because CP DMA is never used on gfx12 
except for cache prefetches.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31168>
 2024-09-14 11:03:44 -04:00
David Heidelberg c5ee7ca4d6 ci/freedreno: mark jobs to be retested with patched 6.11 kernel 
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31177>
 2024-09-14 15:24:04 +09:00
David Heidelberg 52c014a453 ci/freedreno: move disabled a530 entries back to main gitlab-ci.yml 
Fixes: 9442571664 ("ci: separate hiden jobs to -inc.yml files")
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31177>
 2024-09-14 15:20:47 +09:00
Jami Kettunen 849a496b33 nouveau/headers: Fix build without rustfmt 
This is optional elsewhere and seemingly the intention was already to
ignore failures, but it didn't catch FileNotFoundError when rustfmt
isn't even available.

Fixes: 591b5da49b ("nouveau/headers: Run rustfmt on generated files")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30970>
 2024-09-14 04:34:46 +00:00
llyyr 5450306a36 vulkan/wsi/wayland: fix suboptimal flag being ignored with explicit sync 
Signed-off-by: llyyr <llyyr.public@gmail.com>
Fixes: 5f7a5a27ef ("wsi: Implement linux-drm-syncobj-v1")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31122>
 2024-09-13 20:48:05 +00:00
Dylan Baker ed8d1d3c9b anv: if queue is NULL in vm_bind return early 
In the error handling path we end up creating a vk_sync and then later
we vk_sync_wait() on it. If that wait fails somehow we'll end up calling
vk_queue_set_lost(&queue->vk, ...) which would segfault if queue is
NULL.

If we end up in this situation (no queue), return directly whatever the
backend's vm_bind function returned, propagating the error up if
necessary.

Fixes: dd5362c78a ("anv/xe: try harder when the vm_bind ioctl fails")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31048>
 2024-09-13 20:17:40 +00:00
Dylan Baker 0422eed255 iris: Run checks that do not require resources before creating them 
This avoids the need to free the resource if we decide to return early.

Fixes: c8df09ebd4 ("iris: More gracefully fail in resource_from_user_memory")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30306>
 2024-09-13 19:26:57 +00:00
Faith Ekstrand 3a9fe645d7 vulkan: Handle variable-length property arrays more generically 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31119>
 2024-09-13 18:33:11 +00:00
Lucas Stach 5f6ab7dcdf etnaviv: limit number of varyings to fit into VS outputs 
One of the VS output slots is always occupied by the position
output. Limit the number of user visible varyings to fit into
the remaining slots.

This reduces GL_MAX_VARYING_COMPONENTS to 60 on <halti5 GPUs,
which is still enough to meet the GLES3 minimum requirements.

Fixes piglit shaders@glsl-max-varyings.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31032>
 2024-09-13 15:25:07 +00:00
Lucas Stach dcb61d3da5 etnaviv: validate number of VS outputs against GPU limit 
All user defined varyings, the position output and possibly the
point size output need to fit into the GPU specific maximum
number of VS outputs. Check this limitation.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31032>
 2024-09-13 15:25:07 +00:00
Lucas Stach 21a5370f9c etnaviv: fix total varying count assertion 
We can support up to ETNA_NUM_INPUTS varyings. Make sure the assert
allows up to this number.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31032>
 2024-09-13 15:25:07 +00:00
Lucas Stach ea34c7972b etnaviv: support more VS outputs on halti5 GPUs 
Halti5 GPUs doubled the number of available VS outputs, as documented
in rnndb. Double the size of the driver structure and use the size
defines generated by rnndb to emit the correct number of VS output
states, depending on GPU generation.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31032>
 2024-09-13 15:25:06 +00:00
Lucas Stach a71003b1b8 etnaviv: emit all PA shader attributes 
While the rnndb fix increased the size of the driver internal
structures to be able to hold all data for the currently supported
number of varyings, it didn't change the state emission, so only
a subset of the PA shader attribute states was emitted.

Use the define from rnndb to avoid such inconsistencies.

Fixes: 11ffb20b70 ("etnaviv: Update headers from rnndb")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31032>
 2024-09-13 15:25:06 +00:00
Daniel Stone 2dbadf8109 ci: Avoid subshell for executing HWCI_TEST_SCRIPT 
Ensure that $HWCI_TEST_SCRIPT is an executable we can run ourselves, and
run that directly instead of invoking a subshell.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31110>
 2024-09-13 10:12:08 +01:00
Daniel Stone 275727add0 ci/virgl: Special-case llvmpipe parallelisation 
When we're running VirGL/Venus, we sometimes want to invert our
parallelism. As some commands can serialise at the host level, we don't
always want to launch as many test clients as we have CPU cores.
Instead, we want to use our parallelism for llvmpipe's rendering, and
launch only a single test at a time.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31110>
 2024-09-13 10:12:08 +01:00
Konstantin Seurer bacf9752f4 radv: Work around broken terrain in Warhammer III 
Hiding storage support for depth formats forces the game to take a
different, working path for terrain height map initialization.

cc: mesa-stable

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31152>
 2024-09-13 07:48:02 +00:00
Martin Roukala (né Peres) 82946dc152 freedreno/ci: fix the stage of the a750 jobs 
We were accidentally overriding the job stage in .b2c-freedreno-vk-test,
which ended up moving the a750 jobs to the `freedreno` stage instead of
`freedreno-postmerge`.

Fixes: 25c70888a5 ("ci/broadcom: Move manual/nightly jobs to postmerge stage")
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31142>
 2024-09-13 01:51:45 +00:00
Caio Oliveira 5e47c5f94a intel/executor: Fix a couple of memory leaks in the tool 
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31120>
 2024-09-13 01:21:24 +00:00
Ian Romanick 3b13a0018f radv: Use nir_opt_generate_bfi to generate bitfield_select 
v2: Move to radv_optimize_nir_algebraic. Suggested by Georg.

Tested-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31006>
 2024-09-13 00:21:00 +00:00
Ian Romanick 55448cf43a radeonsi: Use nir_opt_generate_bfi to generate bitfield_select 
Not tested.

v2: Move after nir_opt_algebraic. Suggested by Georg.

v3: has_bitfield_select is always enabled on GCN+. Suggested by Georg.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31006>
 2024-09-13 00:21:00 +00:00
Ian Romanick 79bc1da203 r600: Use nir_opt_generate_bfi to generate bitfield_select 
Not tested.

v2: Move after nir_opt_algebraic. Suggested by Georg.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31006>
 2024-09-13 00:21:00 +00:00
Ian Romanick 447dae7c13 intel/brw: Use nir_opt_generate_bfi 
No shader-db changes on any Intel platform.

The "regression" in SEND messages occurs because a loop containing a
SEND is unrolled.

v2: Move after nir_opt_algebraic. Suggested by Georg.

shader-db:

All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19787034 -> 19785933 (<.01%)
instructions in affected programs: 373573 -> 372472 (-0.29%)
helped: 541 / HURT: 6

total cycles in shared programs: 906012612 -> 905626304 (-0.04%)
cycles in affected programs: 58456516 -> 58070208 (-0.66%)
helped: 382 / HURT: 180

fossil-db:

Lunar Lake
Totals:
Instrs: 140671401 -> 140670495 (-0.00%); split: -0.00%, +0.00%
Send messages: 12891430822 -> 12891430834 (+0.00%)
Loop count: 46905 -> 46904 (-0.00%)
Cycle count: 21527511599 -> 21530278999 (+0.01%); split: -0.00%, +0.02%
Spill count: 70728 -> 70766 (+0.05%)
Fill count: 139397 -> 139254 (-0.10%); split: -0.13%, +0.02%
Max live registers: 47512432 -> 47512500 (+0.00%)

Totals from 355 (0.06% of 549270) affected shaders:
Instrs: 878953 -> 878047 (-0.10%); split: -0.18%, +0.08%
Send messages: 19289 -> 19301 (+0.06%)
Loop count: 1243 -> 1242 (-0.08%)
Cycle count: 1434664642 -> 1437432042 (+0.19%); split: -0.06%, +0.25%
Spill count: 15826 -> 15864 (+0.24%)
Fill count: 38454 -> 38311 (-0.37%); split: -0.46%, +0.08%
Max live registers: 52530 -> 52598 (+0.13%)

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 152516575 -> 152516147 (-0.00%); split: -0.00%, +0.00%
Send messages: 7491001 -> 7491013 (+0.00%)
Loop count: 47588 -> 47587 (-0.00%)
Cycle count: 17124433133 -> 17126147156 (+0.01%); split: -0.01%, +0.02%
Max live registers: 31854704 -> 31854764 (+0.00%)

Totals from 402 (0.06% of 633223) affected shaders:
Instrs: 839338 -> 838910 (-0.05%); split: -0.09%, +0.04%
Send messages: 20203 -> 20215 (+0.06%)
Loop count: 1243 -> 1242 (-0.08%)
Cycle count: 1327042160 -> 1328756183 (+0.13%); split: -0.11%, +0.24%
Max live registers: 33237 -> 33297 (+0.18%)

Tiger Lake
*** Shaders only in 'before' results are ignored:
fossil-db/steam-native/wolfenstein_youngblood/b8cefe7f700304c4/fs.32/0
from 1 apps: fossil-db/steam-native/wolfenstein_youngblood

Totals:
Instrs: 150549467 -> 150548952 (-0.00%); split: -0.00%, +0.00%
Send messages: 7495582 -> 7495594 (+0.00%)
Loop count: 46605 -> 46604 (-0.00%)
Cycle count: 15472381586 -> 15472247085 (-0.00%); split: -0.00%, +0.00%
Spill count: 59776 -> 59775 (-0.00%)
Fill count: 103475 -> 103464 (-0.01%)
Scratch Memory Size: 2384896 -> 2383872 (-0.04%)
Max live registers: 31760724 -> 31760787 (+0.00%)
Max dispatch width: 5569928 -> 5569912 (-0.00%)

Totals from 525 (0.08% of 632443) affected shaders:
Instrs: 349074 -> 348559 (-0.15%); split: -0.25%, +0.11%
Send messages: 24355 -> 24367 (+0.05%)
Loop count: 849 -> 848 (-0.12%)
Cycle count: 187080291 -> 186945790 (-0.07%); split: -0.19%, +0.12%
Spill count: 483 -> 482 (-0.21%)
Fill count: 1372 -> 1361 (-0.80%)
Scratch Memory Size: 22528 -> 21504 (-4.55%)
Max live registers: 36705 -> 36768 (+0.17%)
Max dispatch width: 6272 -> 6256 (-0.26%)

Ice Lake
Totals:
Instrs: 151804923 -> 151804396 (-0.00%); split: -0.00%, +0.00%
Send messages: 7553216 -> 7553228 (+0.00%)
Loop count: 46196 -> 46195 (-0.00%)
Cycle count: 15099805668 -> 15099533898 (-0.00%); split: -0.00%, +0.00%
Fill count: 103978 -> 103979 (+0.00%)
Max live registers: 32168254 -> 32168323 (+0.00%)

Totals from 527 (0.08% of 637191) affected shaders:
Instrs: 347482 -> 346955 (-0.15%); split: -0.25%, +0.10%
Send messages: 24586 -> 24598 (+0.05%)
Loop count: 849 -> 848 (-0.12%)
Cycle count: 191147758 -> 190875988 (-0.14%); split: -0.16%, +0.02%
Fill count: 1392 -> 1393 (+0.07%)
Max live registers: 37379 -> 37448 (+0.18%)

Skylake
Totals:
Instrs: 140981504 -> 140980647 (-0.00%); split: -0.00%, +0.00%
Cycle count: 14653477192 -> 14653249734 (-0.00%); split: -0.00%, +0.00%
Fill count: 99636 -> 99637 (+0.00%)
Max live registers: 31472062 -> 31472126 (+0.00%)

Totals from 523 (0.08% of 626432) affected shaders:
Instrs: 335551 -> 334694 (-0.26%); split: -0.26%, +0.01%
Cycle count: 178047284 -> 177819826 (-0.13%); split: -0.14%, +0.02%
Fill count: 1100 -> 1101 (+0.09%)
Max live registers: 36734 -> 36798 (+0.17%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31006>
 2024-09-13 00:21:00 +00:00
Ian Romanick 6a09d33549 nir: Add a pass to generate BFI instructions from logical operations 
Inspired by a commit message in !30934, I set about optimizing the code
generated for nir_copysign. It would be possible to just implement an
opt_algebraic pattern for the specific values used by nir_copysign, but
this casts a slightly larger net.

As noted in a comment in the code, there may be variations of the
pattern that this pass misses. The opt_algebraic pattern would miss them
too.

v2: Use nir_def_replace. Suggested by Alyssa. Allow more "root"
instruction types. Suggested by Georg.

v3: Treat extract_u16(x, 0) as (x & 0x0000ffff), and treat extract_u8(x,
0) as (x & 0x000000ff).

v4: Use nir_scalar. Suggested by Georg.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31006>
 2024-09-13 00:21:00 +00:00
Ian Romanick 057c7c9f53 nir/algebraic: Recognize open-coded bitfield_reverse in XCOM 2 
The XCOM 2 shaders in my shader-db use iadd instead of ior.

No fossil-db changes on any Intel platform.

shader-db:

All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19787210 -> 19787034 (<.01%)
instructions in affected programs: 1187 -> 1011 (-14.83%)
helped: 6 / HURT: 0

total cycles in shared programs: 906024436 -> 906012612 (<.01%)
cycles in affected programs: 72978 -> 61154 (-16.20%)
helped: 6 / HURT: 0

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31006>
 2024-09-13 00:21:00 +00:00
Rhys Perry 97f4250a7c nir: skip opt_loop_peel_initial_break if continue block only has phis 
Doing that optimization wouldn't do anything useful in this case.

nir_block_has_non_copy() is used by opt_loop_peel_initial_break().

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31002>
 2024-09-12 23:36:58 +00:00
Rhys Perry 8410b4cdd6 nir/tests: add some loop peeling tests 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31002>
 2024-09-12 23:36:58 +00:00
Rhys Perry 64ac601049 nir/opt_loop: skip peeling if the loop ends with any kind of jump 
Any kind of jump prevents us from moving it to the top of the loop, not
just breaks.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 6b4b044739 ("nir/opt_loop: add loop peeling optimization")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31002>
 2024-09-12 23:36:58 +00:00
Rhys Perry af3b099e0a nir/opt_loop: skip peeling if the break is non-trivial 
If this nir_if contains continues or other breaks, we can't move it
outside the loop.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 6b4b044739 ("nir/opt_loop: add loop peeling optimization")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31002>
 2024-09-12 23:36:57 +00:00
Rhys Perry 4f44a944bb nir/opt_if: fix fighting between split_alu_of_phi and peel_initial_break 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 6b4b044739 ("nir/opt_loop: add loop peeling optimization")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11822
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31002>
 2024-09-12 23:36:57 +00:00
David Rosca b89d03838e frontends/va: Reset intra refresh in beginPicture 
If app doesn't send updated intra refresh parameters, intra refresh
should be disabled instead of using values from old frame.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:21 +00:00
David Rosca 379dd3ff52 pipe: Remove unused fields in video rate control 
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:21 +00:00
David Rosca 0818ed770d frontends/va: Create encoder at context creation 
Instead of creating it when handling sequence parameter buffer. Drivers
don't use the max_references value (and it was only somewhat correct for
H264) and level is also available from sequence parameters.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
David Rosca 5632a6e24f Revert "frontends/va: Process VAEncSequenceParameterBufferType first in 
vaRenderPicture"

We now set default parameters at context creation, so this is not needed
anymore.

This reverts commit c970a9b663.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
David Rosca 4e38b56d80 frontends/va: Set default encoding parameters at context creation 
Instead of doing it when handling sequence parameter buffer, which could
overwrite previously set values.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
David Rosca 77d5e8ab19 d3d12: Stop using base.level for H264 level_idc 
Instead use the value from sequence parameters.

Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
David Rosca bebda07718 radeonsi/vcn: Stop using base.level for H264 level_idc 
Instead use the value from sequence parameters.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
David Rosca bfc36b0aef radeonsi/uvd_enc: Stop using base.level 
Instead use the value from sequence parameters.
This needs to move the context buffer allocation to first frame
which also allows to remove the temporary surface allocation.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
David Rosca e891717936 radeonsi/vce: Stop using base.level and base.max_references 
Instead use the values from sequence parameters.
This needs to move the context buffer allocation to first frame
which also allows to remove the temporary surface allocation.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
David Rosca 96975bc32f radeonsi/vce,uvd_enc: Stop using obsolete rate control params 
Other drivers don't use these and the values can be derived from other
fields.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30992>
 2024-09-12 22:50:20 +00:00
Georg Lehmann 7fa7812219 nir: merge out of loop decision with nir_can_move_instr logic 
One place to modify instead of two when adding new intrinsics here.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30906>
 2024-09-12 21:49:34 +00:00