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Author SHA1 Message Date
Alyssa Rosenzweig 2a4e4477fc pan/bi: Add bi_layout.c for clause layout helpers 
Figuring out what "shapes" of clauses are kosher happens during
scheduling, not packing, but shouldn't distract the scheduler. So let's
add a new file for these sorts of questions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig c3de28bb49 pan/bi: Remove more artefacts of 2-pass scheduling 
A clause is, by definition, already scheduled.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig 4096be05af pan/bi: Add MUL.i32 to disasm 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig ec8665615f pan/bi: Disassemble pos=0xe 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig a658a4f7a5 pan/bi: Document constant count invariant 
constants + instructions <= 13

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig ac64bf9b20 pan/bi: Move bi_flip_ports out of port assignment 
It's more of a packing fixup than anything scheduler-y, and port
assignment will soon be the domain of the scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig 95e3776d3e pan/bi: Add FILE* argument to bi_print_registers 
In case we need it in general IR printing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig dd96b451f6 pan/bi: Drop struct from bi_registers 
It's a full-fledged part of the IR now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig b042ddef32 pan/bi: Move bi_registers to bi_bundle 
Make it a part of the IR itself.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig 79f30d8a86 pan/bi: Move bi_registers to common IR structures 
Port assignments are critical to scheduling, this can't just live in
bi_pack.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig 59f8f20306 pan/bi: Remove comment about old scheduler design 
I've realized it really has to be 1-pass to be sane.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig 635bf652ed pan/bi: Remove FMA? parameter from get_src 
We can lower away zeroes a bit earlier.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
 2020-05-29 20:34:55 +00:00
Alyssa Rosenzweig 20f6c7a913 panfrost: Preload gl_FragCoord on Bifrost 
It's a precoloured register but we do need to specify in the cmdstream
that we want the preloading to happen.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>
 2020-05-29 20:19:46 +00:00
Alyssa Rosenzweig 1d194f8ac4 panfrost: Set reads_frag_coord as a sysval 
In addition to parsing out the varying. This is needed so it works on
Bifrost as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>
 2020-05-29 20:19:46 +00:00
Alyssa Rosenzweig 52875a34aa panfrost: Don't generate gl_FragCoord varying on Bifrost 
It's treated as a sysval there, so that's silly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>
 2020-05-29 20:19:46 +00:00
Rob Clark 11470fcde2 freedreno/a6xx: fix vsc assert 
Fixes a debug build assert seeing with an android app.  Not quite sure
which path was passing us draw_info w/ instance_count==0.  But we should
just treat non-instanced draws as having a single instance.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5091>
 2020-05-29 19:35:08 +00:00
Kristian H. Kristensen f6f7bc2979 freedreno/a6xx: Program VFD_DEST_CNTL from program stateobj 
This only depends on the generated shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
 2020-05-29 18:59:56 +00:00
Kristian H. Kristensen 7aa809e31c freedreno/a6xx: Create stateobj for VFD_DECODE 
This now only depends on vertex state and we can create it once
up front in pctx->create_vertex_elements_state().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
 2020-05-29 18:59:56 +00:00
Kristian H. Kristensen 8952dd6d99 freedreno/a6xx: Decouple VFD_FETCH and VFD_DECODE 
We used to output a VFD_FETCH entry for each VFD_DECODE, but we can
instead output just one VFD_FETCH per VBO and point multiple
VFD_DECODE entries at the same VFD_FETCH entry.  There's typically
fewer VBOs than vertex elements so this is a small win in itselfs, but
more importantly, the VFD_DECODE state now only depends on program
state.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
 2020-05-29 18:59:56 +00:00
Kristian H. Kristensen c15db8928f freedreno/a6xx: Move per element offset to VFD_DECODE 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
 2020-05-29 18:59:56 +00:00
Samuel Pitoiset 9d645a19eb radv/aco: enable VK_KHR_subgroup_extended_types on GFX8+ 
Should be working now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
 2020-05-29 11:20:58 +00:00
Samuel Pitoiset e22567089c aco: sign-extend input/indentity for 32-bit reduce ops on GFX10 
Because some 16-bit instructions are already VOP3 on GFX10, we use
the 32-bit variants to remove the temporary VGPR and to use DDP with
the arithmetic instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
 2020-05-29 11:20:58 +00:00
Samuel Pitoiset 83dcd1690b aco: allow gfx10_wave64_bpermute with 8-bit/16-bit input 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
 2020-05-29 11:20:58 +00:00
Samuel Pitoiset 8ece71507d aco: allocate a temp VGPR for some 8-bit/16-bit reduction ops on GFX10 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
 2020-05-29 11:20:58 +00:00
Samuel Pitoiset 2e0ea9bcca aco: implement 8-bit/16-bit reductions on GFX10 
Some 16-bit instructions are VOP3 on GFX10 and we have to emit a
32-bit DPP mov followed by the ALU instruction.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
 2020-05-29 11:20:58 +00:00
Samuel Pitoiset 75a730ced5 aco: fix register allocation for subdword instructions on GFX10 
Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
 2020-05-29 11:20:58 +00:00
Bas Nieuwenhuizen ad609bf55a frontend/dri: Implement mapping individual planes. 
It is kinda surprising that

image2 = fromPlanar(image, 2, NULL)
mapImage(..., image2, ...)

does not map the third plane.

This implements that behavior in the case where the DRI frontend
lowers the multi-planar textures.

In the case it doesn't this would need driver support. AFAIU at
least etnaviv is impacted, and while it looks possible, I don't
have the etnaviv knowledge to implement it.

Instead of silently returning weird results (either always plane 0
or possibly something interleaved) this adds an error return on
mapping multi-planar textures otherwise.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5200>
 2020-05-29 09:12:33 +00:00
Vinson Lee a2ee293422 zink: Check fopen result. 
Fix warning reported by Coverity.

Dereference null return value (NULL_RETURNS)
dereference: Dereferencing a pointer that might be NULL fp when calling
fwrite.

Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5235>
 2020-05-29 08:59:19 +00:00
Samuel Pitoiset 7503863fe2 radv/aco: enable VK_EXT_subgroup_size_control 
ACO should already support Wave32 on GFX10 with all shader stages
and CTS pass. RADV currently only allows Wave32 with the compute
shader stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5056>
 2020-05-29 10:12:26 +02:00
Rob Clark 6f39126200 freedreno/a6xx: document LRZ flag buffer 
Doesn't seem to be a big win, although I could still be missing
something in my implementation.  But might as well add the
documentation.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>
 2020-05-29 00:38:28 +00:00
Rob Clark a3947f9d24 freedreno/a6xx: LRZ fix for alpha-test 
Similarly to stencil-test, if alpha-test is enabled, we don't know
necessarily whether the fragment will pass.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3045
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>
 2020-05-29 00:38:28 +00:00
Neha Bhende 838666a41d util: Initialize pipe_shader_state for passthrough and transform shaders 
mesa/st is initializing pipe_shader_state for user define shaders.
This patch intialized pipe_shader_state for all passthough
and transform shaders.

This fixes crashes for several opengl apps. Issue is found in vmware
internal testing

Fixes: f01c0565bb ("draw: free the NIR IR.")

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5240>
 2020-05-28 23:27:53 +00:00
Chris Wilson 034329128b iris: Rename iris_seqno to iris_fine_fence 
Rename iris_seqno to iris_fine_fence, borrowed from si_fine_fence, to
avoid introducing any confusion with any other seqno used for tracking
pipelines.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5233>
 2020-05-28 12:47:19 -07:00
Gert Wollny 682e14d3ea nir: lower_tex: Don't normalize coordinates for TXF with RECT 
v2: remove the option to actually request normalization and its
    application in Intel < Gen6 (Jason)

v3: Also don't lower for query operations (Jason)

Fixes: 1ce8060c25
    nir/lower_tex: support for lowering RECT textures

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5105>
 2020-05-28 18:39:29 +00:00
Samuel Pitoiset 10c4a7cf59 spirv,radv,anv: implement no-op VK_GOOGLE_user_type 
This extension only allows HLSL shader compilers to optionally embed
unambiguous type information which can be safely ignored by the driver.

This fixes a crash with the recent Vulkan backend of Path Of Exile
(it uses the extension without checking if it's supported).

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5237>
 2020-05-28 17:30:24 +02:00
Rhys Perry 01ce7887bf aco: fix 64-bit shared_atomic_exchange 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>
 2020-05-28 10:34:03 +00:00
Rhys Perry 1f2fd9c62e aco: don't reorder barriers in the scheduler 
Unless we're reordering it around a barrier of the same type

No shader-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>
 2020-05-28 10:34:03 +00:00
Rhys Perry e1900ee2c7 aco: preserve more fields when combining additions into SMEM 
Totals from 11 (0.01% of 127638) affected shaders:

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>
 2020-05-28 10:34:03 +00:00
Rhys Perry 95d5c1b8a1 aco: check instruction format before waiting for a previous SMEM store 
Totals from 7 (0.01% of 127638) affected shaders:
CodeSize: 40336 -> 40320 (-0.04%)
Instrs: 7807 -> 7803 (-0.05%)
Cycles: 118588 -> 118344 (-0.21%); split: -0.23%, +0.02%
SMEM: 331 -> 339 (+2.42%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 1749953ea3 ('aco/gfx10: Wait for pending SMEM stores before loads')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>
 2020-05-28 10:34:03 +00:00
Rhys Perry 5ccc7c277c aco: consider SDWA during value numbering 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 23ac24f5b1
   ('aco: add missing conversion operations for small bitsizes')

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5164>
 2020-05-28 09:55:58 +00:00
Rhys Perry 8aa98cebc1 aco: fix interaction with 3f branch workaround and p_constaddr 
The offset was incorrect if we inserted a nop before the p_constaddr.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5164>
 2020-05-28 09:55:58 +00:00
Caio Marcelo de Oliveira Filho bccf2a25a8 intel: Add helper to calculate GPGPU_WALKER::RightExecutionMask 
Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho 78e400d4a5 iris, i965: Update limits for ARB_compute_variable_group_size 
The CS compiler now produces multiple SIMD variants, so the previous
trade-off between "always using SIMD32" and "having a smaller max
invocations" is now gone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho 46b428074f iris, i965: Drop max_variable_local_size 
This was used to decide which SIMD width to generate code for
ARB_compute_variable_group_size.  Now that compiler will generate
multiple SIMD widths, this information is unused.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho 90ec26a800 intel/fs: Generate multiple CS SIMD variants for variable group size 
This will make the GL drivers pick the right SIMD variant for a given
group size set during dispatch.  The heuristic implemented in
brw_cs_simd_size_for_group_size() is the same as in brw_compile_cs().

The cs_prog_data::simd_size field was removed.  The generated SIMD
sizes are marked in a bitmask, which is already used via
brw_cs_simd_size_for_group_size() by the drivers.

When in variable group size, it is OK if larger SIMD shader spill,
since we'd need it for the cases where the smaller one can't hold all
the invocations.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho 9b8347c988 anv: Use new helper functions to pick SIMD variant for CS 
Also combine the existing individual anv helpers into a single one for
all CS related parameters.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho 594374dd8d iris: Use new helper functions to pick SIMD variant for CS 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho c9f4bda6ce iris: Set CS KernelStatePointer at dispatch 
There's an update for INTERFACE_DESCRIPTOR_DATA at dispatch, so we can
just move the KSP assignment there.  This flexibility will later allow
variable group size to pick the right SIMD variant.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho ee0fc0f6dc i965: Use new helper functions to pick SIMD variant for CS 
Also expand the existing i965 helper to return the other CS related
paramters.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00
Caio Marcelo de Oliveira Filho cb26d9c311 intel/fs: Add helper to get prog_offset and simd_size 
This indirection will be used by the variable group size case in a
later change.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>
 2020-05-27 18:16:31 -07:00