AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
204,560 Commits 1 Branch 0 Tags
2a065fc446ef8f458cf5f4e7151db5bb23b4dbbf
Commit Graph

204560 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alyssa Rosenzweig
2a065fc446 agx/nir_lower_gs: use common nir_verts_in_output_prim 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
ea209c98fc agx/nir_lower_gs: drop silly fwd decl 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
ba9f86df51 agx/nir_lower_gs: privatize lower_output_to_var_state 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
d42a92fd93 agx/nir_lower_gs: clean up more state->info 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
470f226ed8 agx/nir_lower_gs: remove silly comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
1017095c5a agx/nir_lower_gs: clean up state/info duplication 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
753e3ba55b asahi,hk: use indirect-local dispatches for GS 
this gets us good workgroup sizes even for indirect draws with GS.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
70c805d863 hk: bump wg sizes for geometry shader 
match GL driver, should help perf.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
164fc8a158 agx/nir_lower_gs: clean comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
b9b6828fda agx/nir_lower_gs: optimize static topologies 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
3da8939197 libagx: factor out _libagx_end_primitive 
so we can use from the cpu.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
d2cc7f38d3 asahi: optimize out empty dispatches 
this occurs with GS lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
b916c38c76 hk: optimize out empty dispatches 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
f6ee36a437 agx: add agx_is_shader_empty helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Alyssa Rosenzweig
f1aeb46a34 nir: factor out nir_verts_in_output_prim helper 
very useful for geometry shader lowering code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34638>
 2025-04-22 12:47:54 +00:00
Vignesh Raman
6c33b1e8c1 ci: replace s3_upload wrapper with ci-fairy s3cp 
Now that ci-fairy s3cp works, replace the s3_upload curl wrapper with
ci-fairy s3cp command.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34550>
 2025-04-22 11:17:16 +00:00
Vignesh Raman
4b3b3d4c70 ci: use MESA_TEMPLATES_COMMIT for ci-fairy install 
Use MESA_TEMPLATES_COMMIT instead of hard-coding the commit hash in
pip install ci-fairy.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34550>
 2025-04-22 11:17:16 +00:00
Vignesh Raman
c4aeef02e2 ci: bump ci-templates 
This is required for ci-fairy s3cp to work.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34550>
 2025-04-22 11:17:16 +00:00
Jayanth Vutukuri
ba64e92641 Add libzstd static library. 
From AOSP 15, getting linking error as
"ld.lld: error: undefined symbol: ZSTD_*" during compilation.
libzstd will link as static library to libelf and this libelf
is being included in mesa3d.

https://android-review.googlesource.com/c/platform/external/elfutils/+/2826411
is the patch from AOSP which is causing build issue.

Signed-off-by: Jayanth Vutukuri <Jayanth.Vutukuri@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34522>
 2025-04-22 11:08:10 +00:00
Boris Brezillon
de78a75f13 panvk: Set .pushDescriptor=true 
We already claim support for VK_KHR_push_descriptor, so we de-facto
support pushDescriptor.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <benjamin.lee@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34640>
 2025-04-22 09:09:57 +02:00
Boris Brezillon
5b7e5db149 panvk: Advertise support for VK_EXT_vertex_input_dynamic_state 
This is already supported, nothing to do here.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <benjamin.lee@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34640>
 2025-04-22 09:09:48 +02:00
Yinjie Yao
2b5ca87927 gallium/pipe: Increase hevc max slice to 600 
According to the spec, increase max supported slices of hevc to 600.

Cc: mesa-stable
Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34632>
 2025-04-22 06:14:21 +00:00
Mel Henning
0f65c858ea nak: Add test for lea disasm. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34334>
 2025-04-21 23:42:55 +00:00
Mel Henning
5f5cb088a9 nak: Disable cbuf textures on blackwell 
There are bound texture forms on blackwell, but they don't correspond
directly to the cbuf textures we have on sm70. Switch to only bindless
for now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34334>
 2025-04-21 23:42:55 +00:00
Mel Henning
fd90b072f1 nak: sm100+ texture encodings 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34334>
 2025-04-21 23:42:55 +00:00
Mel Henning
f70b7d10c2 nak: Fix sm90+ atomg/redg encoding 
and add a test for ld, st, atom

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34334>
 2025-04-21 23:42:55 +00:00
Mel Henning
869452aaf0 nak: Remove range parameter from set_atom_type 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34334>
 2025-04-21 23:42:55 +00:00
Mel Henning
2b82184250 nak: Add nvdisasm_tests 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34334>
 2025-04-21 23:42:55 +00:00
Mel Henning
d31172d092 nvk: Remove dead function nvk_meta_init_render 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34644>
 2025-04-21 22:23:33 +00:00
Mel Henning
2fc4c98aaf nvk: Override render enable for blits and resolves 
Fixes cts tests:

dEQP-VK.conditional_rendering.conditional_ignore.blit_image
dEQP-VK.conditional_rendering.conditional_ignore.blit_image_inverted
dEQP-VK.conditional_rendering.conditional_ignore.resolve_image
dEQP-VK.conditional_rendering.conditional_ignore.resolve_image_inverted

which were introduced in vk-gl-cts commit 4aa277c300

Fixes: 32f2317223 ("nvk: Use meta for doing blits with the 3D hardware")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34644>
 2025-04-21 22:23:33 +00:00
Mel Henning
52085f2a0e nvk: SET_STATISTICS_COUNTER at start of meta_begin 
Ideally, begin/end should be roughly symmetric - the initialization
order should be the reverse of the teardown order.

Fixes: 6f85e6b06b ("nvk: Disable statistics around meta ops")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34644>
 2025-04-21 22:23:33 +00:00
Lina Versace
1bf8542490 anv: Enable VK_EXT_external_memory_acquire_unmodified 
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Change-Id: If0480721f7f1fceec093e4ab7b5c9b712eb62ba1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32295>
 2025-04-21 13:55:32 -07:00
Lina Versace
3613b9c4f7 anv: Fix comment about external queue transitions 
Not all images with DRM format modifiers use
ANV_IMAGE_MEMORY_BINDING_PRIVATE.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Change-Id: Idc6bae70ec7080f96555a85dcdc0ead915b02935
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32295>
 2025-04-21 13:55:27 -07:00
Lina Versace
e87a04c6c1 anv: Assert that only external images have private bindings 
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Change-Id: If2f18d88d48f70a58e236080632e72afb94f5e0b
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32295>
 2025-04-21 13:55:08 -07:00
Sagar Ghuge
0463e14b94 anv: Enable 64bit memory structure mode for RT 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Kevin Chuang
703f29874b intel/bvh/debug: Adapt instance leaf dumping to support 64-bit RT 
Adding a boolean "enable_64b_rt" in anv_accel_struct_header for the
interpret.py to properly decode anv_instance_leaf

Signed-off-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Kevin Chuang
cbc8af4555 intel/bvh: Compile and adapt bvh shaders separately into Xe1/2 and Xe3+ 
This change separate the encode, header, and copy shader into versions
for Xe1/2 and Xe3+, including adding compile options and handling 64bit
version of instance leaf for Xe3+.

Signed-off-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Sagar Ghuge
36433e932b intel/rt: Update BVH instance leaf load for Xe3+ 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Sagar Ghuge
5cd0f4ba2f intel/compiler: Update MemRay data structure to 64-bit 
Rework: (Kevin)
- Fix miss_shader_index offset
- Handle hit group index

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Kevin Chuang
7b526de18f intel/compiler/rt: Calculate barycentrics on demand 
This commit moves the calculation of tri_bary out of
brw_nir_rt_load_mem_hit_from_addr(), and only do the calculation on
demand, since unorm_float_convert can be expensive. We do this for both
Xe1/2 and Xe3+ for consistency.

Signed-off-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Sagar Ghuge
afc23dffa4 intel/compiler: Update MemHit data structure to 64-bit version 
Rework (Kevin):
- Fix inst leaf ptr
- Handle 24bit unorm barycentric coord

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Kevin Chuang
40fb95d51a intel/compiler: Use 24bits for hit_kind on Xe3+ 
For Xe3+, the upper 8 bits of the second dword of a potential hit is
used to store hitGroupIndex0, which is stuffed by the HW. This
hitGroupIndex0 will later be used by the HW again to reconstruct the
whole hitGroupIndex when driver issues a TRACE_RAY_COMMIT.

We were corrupting this hitGroupIndex0 at the driver by setting the
whole dword to hit_kind, which will cause the HW to read a wrong
hitGroupIndex and therefore invoke a wrong closest hit shader. The
behavior can be seen in
dEQP-VK.ray_tracing_pipeline.pipeline_no_null_shaders_flag.gpu.boxes.\*
and dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.\*

This commit changes the driver to only use lower 24bits to store the
hit_kind, and leave the upper 8bits as it.

Signed-off-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Sagar Ghuge
64fd66407b intel/compiler: Pass around intel_device_info parameter in helper 
This will help us to handle code path separately for Xe3+ for updated
64bit memory data structure for RT.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Sagar Ghuge
6deb1950a4 anv: Update RT dispatch globals to use 64bit data structure 
Rework (Kevin)
- Fix Hit/Miss/Resume shader group table value

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Sagar Ghuge
fcd5fe4a75 intel/genxml/xe3: Update 3STATE_BTD field 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33047>
 2025-04-21 20:10:45 +00:00
Mary Guillemard
92afeb37bf panfrost: Take tiler memory budget into account in pan_select_tiler_hierarchy_mask 
On v12+, the hardware report support for 8 levels but
effectively only support up to 4 levels.

In case more than 4 levels are used, it will default to 0xAA when
tile_size is 32x32 or lower, otherwise 0xAC when the tile_size is greater than 32x32.

This patch makes it that we now ensure that the bins can fit inside out
tiler budget and otherwise drop levels until it fit.

This also allows the hardware to decide the hierarchy on v12+
if we know it will fit.

This fixes "dEQP-GLES31.functional.fbo.no_attachments.maximums.all" and
dEQP-GLES31.functional.fbo.no_attachments.maximums.size" on v12+ but
also likely more if we were exhausting the memory budget.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Backport-to: 25.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34559>
 2025-04-21 19:55:59 +02:00
Eric Engestrom
c643f62633 ci: bump to fedora 42 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34626>
 2025-04-21 16:05:11 +00:00
Eric Engestrom
2bcb55f3f6 aco: help clang 20 do some additions and subtractions 
clang 20 complains:

    ../src/amd/compiler/aco_assembler.cpp:837:28: error: writing 1 byte into a region of size 0 [-Werror=stringop-overflow=]
      837 |       vaddr[num_vaddr + i] = reg(ctx, instr->operands.back(), 8) + i + 1;
          |       ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ../src/amd/compiler/aco_assembler.cpp:832:12: note: at offset 5 into destination object ‘vaddr’ of size 5
      832 |    uint8_t vaddr[5] = {0, 0, 0, 0, 0};
          |            ^~~~~
    ../src/amd/compiler/aco_assembler.cpp:837:28: error: writing 1 byte into a region of size 0 [-Werror=stringop-overflow=]
      837 |       vaddr[num_vaddr + i] = reg(ctx, instr->operands.back(), 8) + i + 1;
          |       ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ../src/amd/compiler/aco_assembler.cpp:832:12: note: at offset 6 into destination object ‘vaddr’ of size 5
      832 |    uint8_t vaddr[5] = {0, 0, 0, 0, 0};
          |            ^~~~~
    ../src/amd/compiler/aco_assembler.cpp:837:28: error: writing 1 byte into a region of size 0 [-Werror=stringop-overflow=]
      837 |       vaddr[num_vaddr + i] = reg(ctx, instr->operands.back(), 8) + i + 1;
          |       ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ../src/amd/compiler/aco_assembler.cpp:832:12: note: at offset 7 into destination object ‘vaddr’ of size 5
      832 |    uint8_t vaddr[5] = {0, 0, 0, 0, 0};
          |            ^~~~~

But `i < MIN2(instr->operands.back().size() - 1, 5 - num_vaddr)` means `i` is
at most `5 - num_vaddr - 1`, which means `vaddr[num_vaddr + i]` =>
`vaddr[num_vaddr + 5 - num_vaddr - 1]` => `vaddr[5 - 1]` => `vaddr[4]` which
is within the valid indices.

For some reason, using signed `int` instead allows clang to figure this
out, so let's do that since we don't need the extra range.

While at it, use ARRAY_SIZE(vaddr) instead of hard-coding the same `5`
in several places.

Backport-to: 25.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34625>
 2025-04-21 15:16:02 +00:00
Eric Engestrom
b59b53e824 ci: uprev vkd3d-proton 
078f07f588...7eef0a64e3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34356>
 2025-04-21 11:50:57 +00:00
Eric Engestrom
55199d988a turnip/ci: drop skip of test_vrs_depth_write_dxbc as it no longer hangs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34356>
 2025-04-21 11:50:57 +00:00