2807e27231
radv: set the stream VA for DGC graphics
...
This will be used to emit indirect draws when needed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172 >
2023-11-28 14:07:37 +00:00
88bbdfd23e
radv: remove useless NIR instructions when emitting IBO with DGC
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26172 >
2023-11-28 14:07:37 +00:00
e0a24c7fe0
ac/nir: add kill_layer flag to VS/GS/NGG lowering
...
When the framebuffer state has only 1 layer, the output has no effect.
Reviewed-by: Qiang Yu <yuq825@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26274 >
2023-11-24 15:37:24 +00:00
ad7efdea6e
radv: do not set OREO_MODE to fix rare corruption on GFX11
...
Ported from RadeonSI 3f108e7615samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26333 >
2023-11-23 17:22:04 +00:00
46cc7ffb79
radv: add missing FDCC_CONTROL bits for GFX1103 R2
...
Ported from RadeonSI.
Found by inspection, untested.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26318 >
2023-11-23 13:56:53 +00:00
ab34603115
radv: disable TC-compatible HTILE on Tonga and Iceland
...
According to RadeonSI, TC-compat HTILE have issues on Tonga/Iceland
(first GFX8 chips) and a bunch of games seem to have issues.
Let's disable it instead of using a feature that is known broken.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7101
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3894
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26204 >
2023-11-23 12:55:47 +00:00
b975d4e800
radv: enable meshShaderQueries on GFX10.3
...
GFX11 support will come later.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
6c7265338d
radv: add support for task shader invocations queries on GFX10.3
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
623b7033c5
radv: make some gang functions non-static
...
They will be used to create a gang CS when beginning a query if not
already present.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
1b3efecd56
radv: rework gfx10_copy_gds_query() slightly
...
To prepare for the same function with ACE.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
b7d668a819
radv: add support for mesh shader invocations queries on GFX10.3
...
Also emulated with a GDS atomic counter in shaders.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
48aabaf225
radv: do not harcode the pipeline stats mask for query resolves
...
Otherwise, mesh/task shader invocations would be ignored.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
272ad65397
radv: bump the pipeline state query size to 14 on GFX10.3
...
GFX10.3 doesn't natively support mesh/task shader invocations query
and they need to be emulated in shaders. In order to share more code
between GFX10.3 and GFX11, it's easier to use the same size as GFX11.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
7b13500a99
radv: define new pipeline statistics indices for mesh/task on GFX11
...
GFX11 uses pipeline statistics for mesh/task queries but on GFX10.3
they need to be emulated. Though the number of mesh/task shader
invocations would be copied to the pipeline statistics range to
simplify the implementation.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:49 +00:00
2b93e9a02b
radv: add support for mesh primitives queries on GFX10.3
...
This query is emulated using a GDS atomic counter in shaders.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:48 +00:00
bc6d29b0ca
radv: add radv_physical_device::emulate_mesh_shader_queries for GFX10.3
...
GFX11 supports them natively but not GFX10.3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25950 >
2023-11-21 15:24:48 +00:00
7d1cc5ec3d
radv: rename ps_epilog_inputs to colors for PS epilogs
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26231 >
2023-11-21 08:47:50 +00:00
16a270f646
radv: disable TC-compat htile on GFX9 in some cases
...
Similar to commit a38de4c011https://gitlab.freedesktop.org/mesa/mesa/-/issues/10161
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26263 >
2023-11-20 20:09:44 +00:00
fc044928b2
radv: re-enable sparseResidencyImage3D on POLARIS10+
...
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7214
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26260 >
2023-11-20 08:30:05 +01:00
5932990e08
aco,radv: add aco_is_nir_op_support_packed_math_16bit
...
To be shared by radeonsi and radv.
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Signed-off-by: Qiang Yu <yuq825@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25990 >
2023-11-20 02:20:17 +00:00
d487d9d05b
radv: Use SDMA version instead of gfx_level where possible.
...
The SDMA IP is independent from the GFX IP, so it is technically
wrong to program it based on the GFX level.
This patch changes the RADV SDMA code to use SDMA IP versions
where possible.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com >
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26110 >
2023-11-18 17:11:18 +01:00
24022d5680
radv: Use GPU info for determining SDMA metadata support.
...
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com >
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26110 >
2023-11-18 17:11:15 +01:00
d09ad16fd4
ac: Remove CIK prefix from SDMA opcodes.
...
The vast majority of AMD GPUs (except the very first GCN) have
the same SDMA packet format, so let's just call it SDMA instead
of CIK_SDMA.
(And leave the oldest GPUs with SI_SDMA as they are now.)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com >
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26110 >
2023-11-18 17:11:00 +01:00
6413b860c4
ac: Rename SDMA max copy size macros to reflect SDMA version.
...
This naming is more accurate and closer to the HW.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com >
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26110 >
2023-11-18 17:10:56 +01:00
4d2a3b9573
radv: add radv_disable_trunc_coord option
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25911 >
2023-11-17 15:15:27 +00:00
0d186d356c
amd: Enable boolean subgroup lowering
...
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218 >
2023-11-17 09:45:40 +00:00
c5e6edcddf
radv: check earlier if a graphics pipeline can force VRS per vertex
...
When a graphics pipeline already enables VRS, forcing VRS isn't
possible, check this earlier.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26248 >
2023-11-17 08:39:48 +00:00
61c3796a95
radv: remove redundant check when forcing VRS rates
...
If force_vrs_per_vertex is TRUE, the primitive shading rate varying is
always written.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26248 >
2023-11-17 08:39:48 +00:00
ec82b42944
radv: add a missing async compute workaround for Tonga/Iceland
...
After digging into PAL code again, I figured that Tonga/Iceland are
both affected by a hw bug related to async compute dispatches.
The solution is to change the "threadgroup" dimension mode to the
"thread" dimension mode unconditionally.
This should fix a bunch of issues related to RADV_DEBUG=nocompute on
these GPUs.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7551
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6334
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4679
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26207 >
2023-11-16 11:37:43 +00:00
a31c928c4f
radv: use nir_lower_fp16_casts
...
This correctly implements RTNE f64->f16.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25566 >
2023-11-16 11:02:30 +00:00
4239e13ff6
radv: fix a descriptor leak with debug names and host base descriptor set
...
vk_object_base_finish() needs to be called on the descriptor set in
order to free the debug names.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10098
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26088 >
2023-11-16 09:11:06 +00:00
7718bad474
radv: minor clean up to image view extent override
...
Use the correct image plane consistently. Compressed formats are
single-planar unless emulated. This makes no difference in either case
but makes the code more concise.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26106 >
2023-11-15 20:29:03 +00:00
2533d0a0e2
radv: fix image view extent override for astc
...
When doing ASTC decoding, the image has format VK_FORMAT_ASTC_*, the
internal plane 1 has format VK_FORMAT_R8G8B8A8_UNORM, and the view has
format VK_FORMAT_R8G8B8A8_UINT. It does not need the override for
compressed formats.
Fixes: f97b449e9ehttps://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26106 >
2023-11-15 20:29:03 +00:00
90f8cf0f36
radv/sqtt: Handle monolithic RT pipelines
...
This marks them as Unified in the RGP UI and shows the compute shader
view.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26158 >
2023-11-15 13:46:50 +00:00
b6e09dd521
radv/sqtt: Fix tracing acceleration structure commands
...
ApiRayTracingSeparateCompiled can only used by trace commands.
Fixes: bfb55d0friedrich.vock@gmx.de >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26158 >
2023-11-15 13:46:50 +00:00
627d593443
radv: fix registering queues for RGP with compute only
...
This crashes if the graphics queue isn't created.
Fixes: 930e77e903https://gitlab.freedesktop.org/mesa/mesa/-/issues/10136
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26183 >
2023-11-15 10:41:50 +00:00
538ca7801a
radv: Use shader part caching helpers for VS prolog and PS/TCS epilog.
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26028 >
2023-11-14 13:45:22 +00:00
611545fbfe
radv: Implement helpers for shader part caching.
...
Currently, shader part caching logic is duplicated between VS prolog and
PS/TCS epilogs. This commit introduces a common abstraction to
deduplicate the code.
Additionally, there are a few design decisions that diverts from the
current implementation:
1. A simple mutex is used instead of reader-writer lock. Prolog/epilog
constructions are serialized, removing the need to free duplicate
objects in case of a race.
2. A CS-local cache is used to quickly lookup an entry without holding a
lock. This eliminates locking in over 99% of cases.
3. A set is used to reduce number of allocations.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26028 >
2023-11-14 13:45:22 +00:00
dfc125d423
radv: fix VRS subpass attachment when HTILE can't be enabled on GFX10.3
...
On GFX10.3, VRS rates need to be copied to the HTILE buffer but in some
situations, like for mips, it's not always possible to enable HTILE.
In this case, we can fallback to our internal HTILE buffer and tweak
the depth/stencil registers to use this HTILE buffer.
This fixes a bunch of VRS crashes on GFX10.3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26025 >
2023-11-14 09:02:46 +00:00
f69863fd5a
radv/radeonsi: Forward correct GPU instance to umr.
...
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24578 >
2023-11-13 13:37:27 +00:00
fd80140723
radv: set prolog as_ls if has_ls_vgpr_init_bug=true
...
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com >
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26111 >
2023-11-13 12:09:55 +00:00
ad4b82e192
radv: Pre-mask misaligned_mask for VS prolog.
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023 >
2023-11-13 11:47:42 +00:00
55d21f2f12
radv, aco: Inline struct aco_vs_input_state.
...
Now that we no longer use the radv_vs_input_state pointer, we can simply
inline all the state-related fields.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023 >
2023-11-13 11:47:42 +00:00
3fc3a94bce
radv, aco: Rework VS prolog key handling.
...
The main change is to use struct radv_vs_prolog_key directly instead of
the compressed representation to simplify an upcoming rework in prolog /
epilog caching. In doing so the state struct pointer was replaced with
an inline struct.
Care was also taken to pre-mask all the states with the active attribute
mask and other masks when it makes sense; this ensures that we don't
accidentally use information not hashed into the key during compilation.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023 >
2023-11-13 11:47:42 +00:00
5cc7f54f15
radv: Remove last VS prolog reuse logic.
...
This was broken as the field was never assigned to. This will also be
dropped from the upcoming prolog/epilog lookup rework, as it adds to
code complexity while the benefit of saving one hash table memory access
seems questionable.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023 >
2023-11-13 11:47:41 +00:00
d8a5b76307
aco: Replace aco_vs_input_state.divisors with bitfields.
...
Instead of concrete divisor value, we only pass down the information
whether the divisor is zero or nontrivial (>1).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023 >
2023-11-13 11:47:41 +00:00
9b840df9f6
radv: add drirc options to force re-compilation of shaders when needed
...
On Steam Deck, shaders are pre-compiled for better performance (less
stuttering, less CPU usage, etc). But when a compiler fix needs to be
backported, there is currently no way to handle this properly.
This introduces 3 drirc options
radv_override_{graphics,compute,ray_tracing}_shader_version in order to
force the driver to re-compile pipelines when needed. By default, the
shader version is 0 for all pipelines.
When one drirc is set for a specific game, RADV will re-compile all
pipelines only once with the compiler fix included (because the
pipeline key would be different).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26094 >
2023-11-13 10:47:26 +00:00
88cbe32048
radv: add support for RGP queue events
...
This can be used for analysing queue submissions.
This is still experimental and it can be disabled with
RADV_THREAD_TRACE_QUEUE_EVENT=false if you have issues with it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22779 >
2023-11-13 08:53:10 +00:00
33f4307796
radv: add radv_write_timestamp() helper
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22779 >
2023-11-13 08:53:10 +00:00
661d28cfec
radv: restore sampling CPU/GPU clocks before starting SQTT trace
...
This was removed by mistake in "radv/rgp: Use common trace trigger"
and it introduced a regression with RGP queue events.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22779 >
2023-11-13 08:53:09 +00:00
Samuel Pitoiset