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Frank Binns
206bef1560 docs/features: claim vk 1.2 for pvr 
Although the PowerVR driver isn't passing Vulkan 1.2 conformance yet, all the
required support has been implemented and it's very close to passing all the
tests now.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37761>
 2025-10-10 15:29:03 +00:00
Ashley Smith
a8fb3671e8 panfrost,mesa: Fix versions for EXT_shader_clock 
ES version was missed from extension table

Fixes: 2ce20170 ("mesa: Add support for GL_EXT_shader_clock")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37794>
 2025-10-10 14:58:34 +00:00
Ashley Smith
09d86f9863 panfrost,mesa: Fix versions for EXT_shader_realtime_clock 
ES version was missed from extension table

Fixes: c5500cd1 ("mesa: Add support for GL_EXT_shader_realtime_clock")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37794>
 2025-10-10 14:58:34 +00:00
Hans-Kristian Arntzen
2848901722 radv: Actually fail custom border color sampler creation. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: a52483d9e7 ("radv: fix capture/replay with sampler border color")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37787>
 2025-10-10 14:25:54 +00:00
Samuel Pitoiset
183ed8046c radv: allow VK_FORMAT_S8_UINT with host image copy 
Depth/stencil formats still need to be properly implemented.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
ef900e93fc ac/surface: fix host image copies with stencil-only 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
9a7f1401d8 ac/surface: fix host image copies with 96-bits formats 
Fixes dEQP-VK.image.host_image_copy.simple.r32g32b32_* with
RADV_PERFTEST=hic on RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
d063072182 radv: rename radv_mark_descriptor_sets_dirty() 
Descriptor heaps will be marked as dirty in this function too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:05 +00:00
Samuel Pitoiset
34b3dae3b6 radv: make radv_descriptor_get_va() a static function 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:05 +00:00
Samuel Pitoiset
08dbab0600 radv: rename shader arg descriptor_sets to descriptors 
It's more generic and descriptor heaps will use it too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:03 +00:00
Samuel Pitoiset
609ae4e647 radv: rename indirect_descriptor_sets to indirect_descriptors 
With descriptor heap the driver will also have to emit indirect
descriptor heaps in some cases.

Rename couple of things to make them more generic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:03 +00:00
Samuel Pitoiset
0ff1ce4ac5 radv: use force_indirect_desc_sets when creating RT prologs 
This is cleaner and this field has been added exactly for that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37786>
 2025-10-10 13:22:02 +00:00
Samuel Pitoiset
055b10a75c radv: do not initialize HiZ on transfer queue on RDNA4 
Emitting compute dispatches on SDMA would just hang.

This fixes pending depth/stencil copy tests on transfer queue with
RADV_PERFTEST=transfer_queue.

Fixes: e6c485afb0 ("radv: initialize HiZ metadata during image layout transitions")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37795>
 2025-10-10 12:50:02 +00:00
Martin Roukala (né Peres)
0fbd9e3894 zink/ci: run the a750 job in pre-merge 
In order to fit within the time budget, we parallelize the job.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37758>
 2025-10-10 11:48:51 +00:00
Martin Roukala (né Peres)
33d7be0d9f turnip/ci: squeeze a750-vk into 4 jobs 
The drop in coverage should allow us enable to pre-merge testing on
zink.

While we are at it, I used the result of a previous stress test to
prune the flakes list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37758>
 2025-10-10 11:48:51 +00:00
Lionel Landwerlin
b8ae4ede60 brw: add serialize send stats 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37394>
 2025-10-10 11:19:39 +00:00
Lionel Landwerlin
37a9c5411f brw: serialize messages on Gfx12.x if required 
The Intel EU fusion feature needs to be disabled on SEND messages
where either the texture handle, sampler handle, sampler header is not
identical on fused threads.

This is the case in particular with accesses on non-uniform
texture/sampler handles but could also strike with dynamic
programmable offsets (currently disabled).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37394>
 2025-10-10 11:19:39 +00:00
Lionel Landwerlin
301b71a19f compiler: add an access flag for intel EU fusion 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37394>
 2025-10-10 11:19:39 +00:00
Lionel Landwerlin
c7ac46a1d8 nir/lower_io: add get_io_index_src_number support for image intrinsics 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37394>
 2025-10-10 11:19:39 +00:00
Lionel Landwerlin
ca1533cd03 nir/divergence: add a new mode to cover fused threads on Intel HW 
The Intel Gfx12.x generation of GPU has an architecture feature called
EU fusion in which 2 subgroups run lock step. A typical case where
this happens is a compute shader with 1x1x1 local workgroup size and a
dispatch command of 2x1x1. In that case 2 threads will be run in lock
step for each of the workgroup.

This has been the sources of some troubles in the backend because one
subgroup can run with all lanes disabled, requiring care for SEND
messages using the NoMask flag (execution regardless of the lane mask).

We found out that other things are happening when 2 subgroups run
together :
  - the HW will use the surface/sampler handle from only one subgroup
  - the HW will use the sampler header from only one subgroup

So one of the fused subgroup can access the wrong surface/sampler if
the value is different between the 2 subgroups and that can happen
even with subgroup uniform values.

Fortunately we can flag SEND instructions to disable the fusion
behavior (most likely at a performance cost).

This change introduce a new divergence mode that tries to compute
things divergent between subgroups so that we can flag instructions
accordingly.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37394>
 2025-10-10 11:19:39 +00:00
Simon Perretta
79923115e7 nir/unlower_io_to_vars: keep io bases intact when keeping intrinsics 
nir_recompute_io_bases will modify i/o intrinsics, which is not the
expected behaviour when the keep_intrinsics flag is set.

Fixes: 83aecc8f3f ("mesa/st, nir: commonize unlower_io_to_vars pass")
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37725>
 2025-10-10 11:53:24 +01:00
Kenneth Graunke
dd9e002129 brw: Fix mesh shader asserts in clip/cull distance setting 
mesh doesn't use brw_vue_prog_data.  Also, I had been catching TCS
shaders here, and shouldn't.

Fixes: bf76e86bc8 ("brw: Refactor clip/cull distance mask setting into a helper")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37809>
 2025-10-10 09:51:26 +00:00
Juan A. Suarez Romero
9f45f09b86 glsl: use array element type to validate assignment 
When comparing an vec3 and a vec4 array, scalar type is the same for
both (float). Instead use the array element type to compare (that is,
vec3 vs vec4).

Fixes
spec@glsl-1.20@compiler@invalid-vec4-array-to-vec3-array-conversion.vert
piglit test.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37783>
 2025-10-10 09:19:55 +00:00
Job Noorman
6d59a3e3e7 nir/lower_alu: use Knuth's Algorithm M for [iu]mul_high 
This significantly simplifies the handling of signed numbers as the same
code path can handle signed and unsigned numbers by simply using ishr
instead of ushr for some of the shifts. For both cases, the number of
additions and shifts are also reduced.

Note that LLVM uses the same algorithm.

fossil-db stats for Turnip:

Totals from 4849 (2.94% of 164705) affected shaders:
MaxWaves: 52318 -> 52332 (+0.03%); split: +0.04%, -0.02%
Instrs: 5262458 -> 5218922 (-0.83%); split: -0.87%, +0.05%
CodeSize: 10831900 -> 10655170 (-1.63%); split: -1.64%, +0.01%
NOPs: 829481 -> 836010 (+0.79%); split: -0.95%, +1.74%
MOVs: 176187 -> 173788 (-1.36%); split: -3.27%, +1.91%
COVs: 104096 -> 86543 (-16.86%); split: -16.87%, +0.01%
Full: 90434 -> 90158 (-0.31%); split: -0.33%, +0.03%
(ss): 131091 -> 130866 (-0.17%); split: -0.87%, +0.70%
(sy): 55550 -> 55769 (+0.39%); split: -0.92%, +1.32%
(ss)-stall: 406003 -> 407194 (+0.29%); split: -1.10%, +1.39%
(sy)-stall: 1668213 -> 1678082 (+0.59%); split: -1.31%, +1.90%
Preamble Instrs: 1105270 -> 1067290 (-3.44%); split: -3.50%, +0.06%
Constlen: 423776 -> 423560 (-0.05%)
Last helper: 1038202 -> 1035540 (-0.26%); split: -0.42%, +0.16%
Last baryf: 38908 -> 38632 (-0.71%)
Subgroup size: 336640 -> 336832 (+0.06%)
Cat0: 916209 -> 922848 (+0.72%); split: -0.87%, +1.59%
Cat1: 282813 -> 262845 (-7.06%); split: -7.49%, +0.43%
Cat2: 2198715 -> 2183012 (-0.71%); split: -0.72%, +0.01%
Cat3: 1390914 -> 1376421 (-1.04%)
Cat7: 123127 -> 123116 (-0.01%); split: -0.24%, +0.23%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37793>
 2025-10-10 05:31:17 +00:00
Job Noorman
18f69890d1 nir: add nir_shr builder 
Sometimes we need to select between ishr/ushr based some condition; this
builder makes this less verbose.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37793>
 2025-10-10 05:31:17 +00:00
Olivia Lee
10a8defecc util/macros: coerce likely/unlikely to bool even without __builtin_expect 
Coercing the argument to a bool when we have __builtin_expect but
leaving it unmodified otherwise is a recipe for really subtle bugs. I
don't know if any bugs like that exist currently, but I almost
introduced one in panfrost.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37801>
 2025-10-10 01:37:28 +00:00
Lionel Landwerlin
196c7903b9 anv: fix companion usage for emulated image 
We need to return true if we need the companion batch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e60416b4e4 ("anv: use companion batch for operations with HIZ/STC_CCS destination")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37797>
 2025-10-09 21:38:33 +00:00
Kenneth Graunke
bb096b0f12 brw: Use BITFIELD_{MASK,RANGE} in clip/cull distance mask handling code 
Suggested by Alyssa.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
 2025-10-09 13:20:04 -07:00
Kenneth Graunke
bf76e86bc8 brw: Refactor clip/cull distance mask setting into a helper 
This was copy pasted between 4 different stages.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
 2025-10-09 13:20:03 -07:00
Kenneth Graunke
b3c511592a brw: Replace type_size_xvec4 with glsl_count_attribute_slots 
This is nearly identical, except for bindless sampler/texture/image
handling.  But we only use it for inputs/outputs, not uniforms, where
there are no bindless handles to worry about.

Deletes a lot of mostly-duplicated code.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
 2025-10-09 13:20:00 -07:00
Kenneth Graunke
a12f117cef brw: Stop using type_size_dvec4 for fragment shader outputs 
There are no 64-bit renderable formats so we can't have FS outputs that
are dvecs.  This dates back to 2016 and a ton of the backend has been
rewritten, so I think whatever this was trying to solve is no longer a
problem.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
 2025-10-09 13:19:56 -07:00
Olivia Lee
d600cd4c91 vtn_bindgen2: use anonymous namespace to avoid name collisions 
All vtn_bindgen2-generated files use the same 'vtn_bindgen_dummy' struct
name. When linking more than one file (like in panfrost), the
constructor and destructor symbols collide and every instance ends up
running the same initialization. In panfrost, this results in us
dropping any printf format strings that don't occur in v6.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: b7447a94c8 ("vtn: add vtn_bindgen2 tool")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37798>
 2025-10-09 19:18:58 +00:00
Lucas Fryzek
3a124ac82a anv: Enable VK_ANDROID_external_format_resolve 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Lucas Fryzek
eb70d66228 anv: Add external format resolve operation using blorp 
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Lucas Fryzek
48b63ee90d vulkan/runtime: Add logic to set external format resolve mode 
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Lucas Fryzek
131f4ca7cc vulkan/android: Add rp_attachment_has_external_format helper 
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Lucas Fryzek
bbcafa630f anv: Modify anv feature (dis)enable code to match other drivers 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Lucas Fryzek
1b333251c4 anv: Enable R10X6 & R10X6G10X6 unorm formats 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Lucas Fryzek
232f8c42f7 anv: Assert that we only import ahb image with one layer 
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Lucas Fryzek
9493f7781d vulkan/runtime: Error if ahb has more than one layer 
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
 2025-10-09 18:42:13 +00:00
Emma Anholt
d01aae2fb1 nir: Add a shader bisect tool. 
When you're trying to figure out what shader some NIR pass broke, use
nir_shader_bisect_select() to decide between NIR pass behaviors, and then
nir_shader_bisect.py will help you automatically bisect down to which
source_blake3 is at fault.  Once it's identified, it prints you a C call
you can use for selecting that shader specifically, which you can use for
continuing on in your debugging.

On a test I was looking at, this took 10 steps to bisect 134 shaders down
to the source_blake3 of the NIR shader in question.

This idea is heavily lifted from Job Noorman's ir3_shader_bisect.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37468>
 2025-10-09 17:56:30 +00:00
Yiwei Zhang
6d2b2963a2 calendar: fix 25.3 branch names 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37796>
 2025-10-09 10:12:05 -07:00
Yiwei Zhang
98a6825d35 panvk: fix to clear FPK with incompatible blend modes 
When there's only blend mode updates (e.g. CB_BLEND_EQUATIONS not
covered by fs_user_dirty check), we have to set dcd0_dirty for the
relevant CB updates. Otherwise, we might miss to clear FPK. On the
other hand, this also optimizes to set FPK in the reverse mutation, so
that new draws no longer depending on the previous tile buffer can
benefit from FPK.

Cc: mesa-stable
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37760>
 2025-10-09 16:22:35 +00:00
Romaric Jodin
c8b10b4512 meson: add vk_enum_defines.h to idep_vulkan_util_headers 
Adding vk_enum_defines.h to idep_vulkan_util_headers to help
ninja-to-soong generate correct rules for the Android build system.

Without it, ninja-to-soong is not able to figure out that this file is
needed by targets depending on idep_vulkan_util_headers, leading to
build errors with the file missing.

Ref #14072

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37789>
 2025-10-09 14:47:11 +00:00
Alyssa Rosenzweig
ee671cf4f7 intel/nir_blockify_uniform_loads: use helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
6b006db492 brw/nir_lower_storage_image: use helper 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
e3b6440b39 brw/nir_lower_shader_calls: use helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
ec8ed69131 brw/nir_lower_sample_index_in_coord: use helpers 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
544a739abc brw/nir_lower_fs_barycentrics: avoid nir_def_rewrite_uses_after 
replace is preferred when appropriate & should be faster. after is when
you use the result in your lowering itself.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:19 -04:00
Alyssa Rosenzweig
4fe8c19862 brw/nir_lower_alpha_to_coverage: eliminate goto 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
 2025-10-09 09:50:19 -04:00