1cd2bb58fb
pco: skip vector coalescing if ssa srcs are repeatedly referenced
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:57 +00:00
9d23d92afa
pco: handle frag/point coords sysvals
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:56 +00:00
74d50d7720
pco: add support for load_ubo
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:56 +00:00
d17d97a867
pco: remove per-device specialization of SPIR-V/NIR options
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:55 +00:00
6ff964dd03
pvr, pco: initial descriptor rework
...
Use more Vulkan runtime/common functions.
Properly use the descriptor pool.
Start to remove legacy/unused constructs from PDS generation.
Support for UBO descriptors.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:55 +00:00
38d581d842
pvr: drop pvr_lower_nir
...
This pass can now remain in the compiler as Vulkan-specific data will be
abstracted into the compiler-driver interface.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:54 +00:00
08222dc461
pvr: add missing refcounting for descriptor set layouts
...
Do this by switching to vk_descriptor_set_layout and making use of the helper
functions. This also has the bonus of less code in the driver.
Fixes a segfault seen when running glmark2-es2-wayland.
Signed-off-by: Frank Binns <frank.binns@imgtec.com >
Co-authored-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:54 +00:00
51a3372ff2
pvr: clarify image/sampler state word packing
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:53 +00:00
8b8e33106d
pco: additional helper functions for address refs
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:53 +00:00
e7d50a6781
pco: add pco nir algebraic pass boilerplate and basic lowering/opts
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:53 +00:00
087d439a52
pco: run dce pass until no more progress is made
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:52 +00:00
6ad0b59cc8
Revert "pvr: Implement VK_EXT_memory_budget"
...
This reverts commit 97efa57531luigi.santivetti@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:52 +00:00
a22ad99bdd
pvr: set device features/props/extensions to Vulkan 1.0 minimums (unless implemented)
...
The KHR_shader_expect_assume dEQP tests use dynamic rendering without
first checking that the driver supports 1.3 or the
KHR_dynamic_rendering extension
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:52 +00:00
ac2460bb3c
pvr: commonize limits
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:51 +00:00
b13fe4e7a7
pco: commonise pass macro, use on opt subpasses
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:51 +00:00
765e9d837d
pco, pygen: validate phases and io allocations for ops
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:50 +00:00
c201332fff
pco, pygen: iterators for igrps and the instrs they contain
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:50 +00:00
04f3b3a5c9
pco, pygen: track valid phases and io allocations for ops
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:49 +00:00
05912bcb60
pco: initial legalize pass/validation to handle hw restrictions
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:49 +00:00
4402649b01
pco, pygen: track which hw srcs map to op srcs/dests
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:49 +00:00
4e171bcf89
pco, pygen: further abstract src/dest references
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:48 +00:00
d552d5b278
pco, pygen: add support for bitwise logical ops
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:48 +00:00
c2787d1d12
pco, pygen: add support for unpck and conversions
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:47 +00:00
8c379b0c3e
pco, pygen: add support for dma ld and add64_32
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:47 +00:00
ff51ba7e43
pco, pygen: add support for tst, movc instructions and s{lt,ge,eq,ne} ops
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:47 +00:00
f1b63fe3f9
pco, pygen: add fdiv/frcp support
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:46 +00:00
7fb0223c93
pco, pygen: support enum mappings for instances of two bitsets
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:46 +00:00
88ac50cbb2
pco, pygen: amend translation of srcs/dests with no mods
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:45 +00:00
e9c7afc217
pco, pygen: rework isa gen to support multi-instruction groups
...
- Split encode and group mappings to allow the former to be re-used.
- Add custom zero value mapping for bitset enums.
- Enable optional enum mapping for ref mods (previously just op mods).
- Commonize nop/nop.end.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:45 +00:00
11238774a4
pco: amend z/w usage code
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:45 +00:00
6ca0f828fa
pco: amend source validation tracking
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:44 +00:00
18ef63e365
pco: drop shader binary finalizing
...
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com >
Acked-by: Frank Binns <frank.binns@imgtec.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998 >
2025-07-08 23:10:44 +00:00
b9a9f6cd53
meson: Allow unnecessary_transmutes for bindgen
...
Otherwise I get hundreds of "unnecessary transmute" warnings
on rustc 1.88.0
Cc: mesa-stable
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35874 >
2025-07-08 20:51:44 +00:00
0eb67508bd
vulkan/util: add vk_realloc2
...
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com >
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com >
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35998 >
2025-07-08 20:22:13 +00:00
8d22eb960b
brw/disasm: Fix Gfx11 3src-instructions dst register disassembly
...
The conversion from bit value to register file type is already done
by the brw_eu_inst_3src_a1_dst_reg_file in the FFC macro now, so doing it
again produced incorrect results.
Fixes: e7179232https://gitlab.freedesktop.org/mesa/mesa/-/issues/13141
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35960 >
2025-07-08 19:49:09 +00:00
5b619cc4b0
freedreno: Advertise external_only if we can't render
...
Don't claim we can render to formats unconditionally.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:45 +00:00
29c342649d
freedreno: Avoid unnecessarily aligning to gmem_align_w
...
If we aren't going to be rendering to this resource, we don't need to
take gmem alignment into account.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:45 +00:00
70fe77f61b
freedreno/a6xx: Allow suboptimal sampling formats when requested
...
We prefer PoT block sizes for various reasons, but if we are asked to
import 12/24/48b formats for sampling we can do so.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:45 +00:00
63b33eb4d9
dri: Correct handle-usage flags
...
If we can only import for sampling from, don't tell the driver that we
want to render to the handle.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:43 +00:00
ba7454a155
dri2+gallium: Support to import suboptimal formats
...
In some cases a format may be supported in a more limited way by the
hardware. For example, formats with NPoT pixel sizes. A driver might
normally prefer that mesa/st use R8G8B8X8 rather than R8G8B8. But if
the user wants to (dma-buf/etc) import R8G8B8, it is still possible,
and in this case zero copy is more important.
So add a PIPE_BIND_x flag as a hint to the driver when checking if
a format is supported.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Reviewed-by: Marek Olšák <marek.olsak@amd.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:43 +00:00
2870addd15
freedreno/fdl: Add support for RGB888/BGR888 pipe formats in render buffer creation
...
This enables the rendering of RGB/BGR 24-bit format buffers directly
onto the framebuffer. For RGB888, support already exists for vertex and
texture formats, so render buffer format support has been added. For
BGR888, support for vertex, texture, and render buffer formats has been
added. The internal format chosen for both RGB888 and BGR888 is GL_RGB8.
Change-Id: I0557389dba05d3b44d7b935f02683df17e41fbd2
Signed-off-by: Petar G. Georgiev <quic_petarg@quicinc.com >
Signed-off-by: Lakshman Chandu Kondreddy <quic_lkondred@quicinc.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:43 +00:00
67a980ee95
freedreno/layout: Support for NPoT formats
...
Three component formats don't get UBWC, but do get their pitch aligned
to the next PoT size.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:43 +00:00
34b61a23d2
freedreno/a6xx: Don't try to tile NPoT formats
...
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982 >
2025-07-08 19:05:43 +00:00
02d0b6bfa6
llvmpipe: Allocate some stuff on demand
...
The memory footprint of the table has gotten quite out of hand (>3GB in
Control DX12). This patch brings that number down to around 3MB.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35959 >
2025-07-08 18:22:12 +00:00
da1c8f6373
llvmpipe: Move allocation out of compile_sample_functions
...
Makes it much more clear what is happening.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35959 >
2025-07-08 18:22:12 +00:00
5270b65d3e
agx: lower alu after scalarizing
...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989 >
2025-07-08 17:09:16 +00:00
fc95397957
nir/lower_alu: optimize min/max signed zeros
...
we don't usually need a multi-instruction lowering.
with the agx change in the next commit, honeykrisp results:
Totals from 3589 (6.64% of 54019) affected shaders:
MaxWaves: 3598144 -> 3598400 (+0.01%); split: +0.02%, -0.01%
Instrs: 1445830 -> 1332394 (-7.85%)
CodeSize: 10696356 -> 9742130 (-8.92%)
Fills: 721 -> 723 (+0.28%); split: -0.14%, +0.42%
Scratch: 3980 -> 3968 (-0.30%)
ALU: 1156426 -> 1043198 (-9.79%)
FSCIB: 1156426 -> 1043196 (-9.79%)
IC: 267202 -> 267166 (-0.01%)
GPRs: 208765 -> 208712 (-0.03%); split: -0.16%, +0.14%
Uniforms: 683643 -> 683677 (+0.00%); split: -0.01%, +0.01%
Preamble instrs: 1163325 -> 1159314 (-0.34%)
control results alone:
Totals:
Instrs: 110168 -> 107171 (-2.72%)
Totals from 71 (22.26% of 319) affected shaders:
Instrs: 48895 -> 45898 (-6.13%)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Marek Olšák <maraeo@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989 >
2025-07-08 17:09:16 +00:00
042adf3cc5
nir/opt_algebraic: optimize signed pow in Control
...
used in a post-processing shader which goes 896 instrs -> 749 instrs.
In my Control fossil:
Totals from 2 (0.63% of 319) affected shaders:
Instrs: 2078 -> 1841 (-11.41%)
CodeSize: 14540 -> 12800 (-11.97%)
ALU: 1779 -> 1626 (-8.60%)
FSCIB: 1779 -> 1626 (-8.60%)
Uniforms: 370 -> 372 (+0.54%)
In radv_fossils, there are affected shaders in Dredge.
Totals from 4 (0.01% of 54019) affected shaders:
Instrs: 2306 -> 2294 (-0.52%)
CodeSize: 16594 -> 16534 (-0.36%)
ALU: 2010 -> 2004 (-0.30%)
FSCIB: 2010 -> 2004 (-0.30%)
Uniforms: 1138 -> 1146 (+0.70%)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989 >
2025-07-08 17:09:16 +00:00
2765017553
nir: fuse ffma even with float controls
...
The fmul+fadd -> fma rules in nir_opt_algebraic are marked imprecise,
because they are a contraction. However, they respect signed zero/Inf/NaN rules.
As such, it is legal to do this fusion with shader float controls as long as the
exact bit is not set (mapping to SPIR-V NoContract).
Unfortunately, NIR's imprecise rules do not distinguish between contraction
issues versus float special case issues, forcing nir_search to skip all
imprecise rules when any shader float control modes are used. This notably
affects DXVK, which sets shader float controls to get D3D11 float behaviour and
hence loses FMA fusing.
Therefore, we plumb in the exact bit to express NoContract independent of the
float controls, and weaken the requirement for fma fusion to allowable
contraction. For fma splitting, it's a similar issue, as inexact GLSL fma in
SPIR-V is just a multiply add that we're allowed to contract rather than the
real deal.
Drivers that use their own FMA fusing passes (notably, Intel and AMD) are
unaffected, but DXVK-capable drivers using fuse_ffma should like this. Results
on hk shown:
Totals from 2194 (4.06% of 54019) affected shaders:
MaxWaves: 2174272 -> 2175936 (+0.08%); split: +0.08%, -0.01%
Instrs: 1173283 -> 1131494 (-3.56%); split: -3.57%, +0.01%
CodeSize: 8568168 -> 8381724 (-2.18%); split: -2.18%, +0.01%
Spills: 1094 -> 747 (-31.72%)
Fills: 988 -> 681 (-31.07%)
Scratch: 4444 -> 3820 (-14.04%)
ALU: 953032 -> 913149 (-4.18%); split: -4.19%, +0.01%
FSCIB: 953032 -> 913149 (-4.18%); split: -4.19%, +0.01%
IC: 215398 -> 215274 (-0.06%)
GPRs: 139865 -> 139032 (-0.60%); split: -1.56%, +0.96%
Uniforms: 414886 -> 414466 (-0.10%); split: -0.14%, +0.04%
Preamble instrs: 646398 -> 644017 (-0.37%); split: -0.43%, +0.07%
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989 >
2025-07-08 17:09:16 +00:00
2c51a8870d
nir: add nir_vectorize_cb callback parameter to nir_lower_phis_to_scalar()
...
Similar to nir_lower_alu_width(), the callback can return the
desired number of components for a phi, or 0 for no lowering.
The previous behavior of nir_lower_phis_to_scalar() with lower_all=true
can be elicited via nir_lower_all_phis_to_scalar() while the previous
behavior with lower_all=false now corresponds to nir_lower_phis_to_scalar()
with NULL callback.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Mel Henning <mhenning@darkrefraction.com >
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35783 >
2025-07-08 15:33:59 +00:00
Simon Perretta