094ddc35cc
anv: constify some helpers
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36512 >
2025-08-01 11:35:08 +00:00
18f234a8a2
anv: avoid looking at the pipeline to flush push descriptors
...
We do this at the cost of recomputing some values that where available
on the pipeline at vkCmdBindPipeline() time.
We can look at the shaders on graphics/compute which will work nicely
with the runtime.
The runtime doesn't have support for ray tracing pipelines so we keep
using them.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36512 >
2025-08-01 11:35:07 +00:00
8d5cb999f9
anv: store layout_type on the bind_map for convenience
...
Pipeline layout is going away.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36512 >
2025-08-01 11:35:06 +00:00
240482f5f5
anv: break ANV_CMD_DIRTY_PIPELINE into each stage
...
Since the pipeline concept is going to go away into the runtime, this
gives us finer control over runtime flushing.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36512 >
2025-08-01 11:35:04 +00:00
ddf2aa3a4d
build: avoid redefining unreachable() which is standard in C23
...
In the C23 standard unreachable() is now a predefined function-like
macro in <stddef.h>
See https://android.googlesource.com/platform/bionic/+/HEAD/docs/c23.md#is-now-a-predefined-function_like-macro-in
And this causes build errors when building for C23:
-----------------------------------------------------------------------
In file included from ../src/util/log.h:30,
from ../src/util/log.c:30:
../src/util/macros.h:123:9: warning: "unreachable" redefined
123 | #define unreachable(str) \
| ^~~~~~~~~~~
In file included from ../src/util/macros.h:31:
/usr/lib/gcc/x86_64-linux-gnu/14/include/stddef.h:456:9: note: this is the location of the previous definition
456 | #define unreachable() (__builtin_unreachable ())
| ^~~~~~~~~~~
-----------------------------------------------------------------------
So don't redefine it with the same name, but use the name UNREACHABLE()
to also signify it's a macro.
Using a different name also makes sense because the behavior of the
macro was extending the one of __builtin_unreachable() anyway, and it
also had a different signature, accepting one argument, compared to the
standard unreachable() with no arguments.
This change improves the chances of building mesa with the C23 standard,
which for instance is the default in recent AOSP versions.
All the instances of the macro, including the definition, were updated
with the following command line:
git grep -l '[^_]unreachable(' -- "src/**" | sort | uniq | \
while read file; \
do \
sed -e 's/\([^_]\)unreachable(/\1UNREACHABLE(/g' -i "$file"; \
done && \
sed -e 's/#undef unreachable/#undef UNREACHABLE/g' -i src/intel/isl/isl_aux_info.c
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36437 >
2025-07-31 17:49:42 +00:00
4de638ae1e
intel: Enable CCS_E on linear surfaces on Xe2+
...
Allow CCS for non-display linear surfaces in isl_surf_supports_ccs().
We're going to rely more on the helper to determine CCS-enabling for Xe2
on iris.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32120 >
2025-07-21 18:36:31 +00:00
ac78693b6a
intel/genxml: rename body field
...
So that the body field has the same name in COMPUTE_WALKER &
EXECUTE_INDIRECT_DISPATCH.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36146 >
2025-07-16 01:01:11 +00:00
29fc96cb80
anv: Add GPU breakpoint before/after specific compute dispatch call
...
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13089
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35353 >
2025-07-07 17:43:41 +00:00
4830aec8ad
anv: Reduce compiled code for Wa_16018063123
...
Wa_16018063123 is not a workaround that depends on stepping, so we
can use the INTEL_WA_16018063123_GFX_VER macro to reduce code generate
for non affected platforms.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700 >
2025-07-03 14:09:13 +00:00
926e6a94ad
anv: Do not emit batch_emit_fast_color_dummy_blit() for video engine
...
Wa_16018063123 don't apply to video engine also video engine don't
support XY_FAST_COLOR_BLT.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Fixes: ec43c20182jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700 >
2025-07-03 14:09:12 +00:00
4618a99a4c
anv: Flush before invalidate aux map in copy and video engines
...
BSpec: 43904
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 46f5359238jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700 >
2025-07-03 14:09:12 +00:00
e68f81eaf6
anv: Read the correct register for aux table invalidation when in GPGPU mode in render engine
...
For 3D or GPGPU modes the same render engine should be used, CCS
register should only be used when using compute engine.
Fixes: 46f5359238ivan.briano@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700 >
2025-07-03 14:09:12 +00:00
32b53a7c6a
anv: fix clears on single aspect of YCbCr images
...
Fixes vkd3d-proton's test_planar_video_formats
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35679 >
2025-06-23 05:45:25 +00:00
4dad9d443b
anv: fix valgrind warning
...
Found when running
KHR-Single-GL46.arrays_of_arrays_gl.InteractionArgumentAliasing2_var_type_index_4
with zink/anv :
Test case 'KHR-Single-GL46.arrays_of_arrays_gl.InteractionArgumentAliasing2_var_type_index_4'..
==22722== Thread 3 glcts:zfq0:
==22722== Uninitialised byte(s) found during client check request
==22722== at 0x134A8D51: anv_batch_bo_finish (anv_batch_chain.c:350)
==22722== by 0x134ACD3E: anv_cmd_buffer_end_batch_buffer (anv_batch_chain.c:1114)
==22722== by 0x13CECB30: end_command_buffer (genX_cmd_buffer.c:3467)
==22722== by 0x13CECB7B: gfx12_EndCommandBuffer (genX_cmd_buffer.c:3478)
==22722== by 0x6FFA343: submit_queue (zink_batch.c:739)
==22722== by 0x672684B: util_queue_thread_func (u_queue.c:294)
==22722== by 0x6790976: impl_thrd_routine (threads_posix.c:43)
==22722== by 0x579BAA3: start_thread (pthread_create.c:447)
==22722== by 0x5828A33: clone (clone.S:100)
==22722== Address 0x94ac840 is 2,112 bytes inside a block of size 8,192 client-defined
==22722== at 0x134A04C7: anv_bo_pool_alloc (anv_allocator.c:1311)
==22722== by 0x134A8772: anv_batch_bo_create (anv_batch_chain.c:262)
==22722== by 0x134AB6BC: anv_cmd_buffer_init_batch_bo_chain (anv_batch_chain.c:877)
==22722== by 0x134BCC4C: anv_create_cmd_buffer (anv_cmd_buffer.c:146)
==22722== by 0x152FEBE4: vk_common_AllocateCommandBuffers (vk_command_pool.c:218)
==22722== by 0x133FEA1D: vkAllocateCommandBuffers (trampoline.c:1950)
==22722== by 0x6FF8AE4: create_batch_state (zink_batch.c:367)
==22722== by 0x6FF91B5: get_batch_state (zink_batch.c:495)
==22722== by 0x6FF91DB: zink_reset_batch (zink_batch.c:504)
==22722== by 0x6FF9424: zink_start_batch (zink_batch.c:537)
==22722== by 0x706C01D: zink_context_create (zink_context.c:5647)
==22722== by 0x60403A6: st_api_create_context (st_manager.c:978)
==22722==
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: d21e7e5a9fsagar.ghuge@intel.com >
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35549 >
2025-06-16 18:26:30 +00:00
d0608425f4
anv: handle REMAINING_LAYERS with 3D images & maintenance9
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 9a1485ec5ctapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35487 >
2025-06-12 11:34:33 +00:00
9a1485ec5c
anv: missing bit from maintenance9
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 595889018atapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35467 >
2025-06-12 09:14:20 +03:00
595889018a
anv: implement VK_KHR_maintenance9
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35381 >
2025-06-11 14:09:56 +00:00
b2ad1333d0
anv: Use genX(set_fast_clear_state)() in transition_depth_buffer()
...
Simplify transition_depth_buffer() by reusing a function to update the
fast-clear value instead of open-coding that logic.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329 >
2025-06-09 17:40:21 +00:00
e0bce5650c
anv: Move the gfx9 sRGB sampling clear color code
...
Simplify set_image_clear_color() by restricting the gfx9-specific code
to the gfx9 #ifdef.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329 >
2025-06-09 17:40:21 +00:00
d21e7e5a9f
anv: Query sampler offset in set_image_clear_color()
...
Enables set_image_clear_color() to be used in transition_depth_buffer()
in a future commit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329 >
2025-06-09 17:40:21 +00:00
1820db80d6
anv: Fix an assert for ISL_FORMAT_RAW clear color update
...
We meant to count the number of bits, not bytes.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329 >
2025-06-09 17:40:21 +00:00
27a5d84632
intel/isl: Fix isl_get_sampler_clear_field_offset()
...
Through testing, I've found that the sampler will fetch the clear color
pixel from the converted clear color field in more cases. So, stop
reporting the raw dword offset for them:
* On gfx12.5, for 32-bpc color images.
* On gfx11-12.0, for 64-bpp color images.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329 >
2025-06-09 17:40:20 +00:00
248b8cb8c5
anv: drop anv_can_hiz_clear_ds_view in favor of anv_can_hiz_clear_image
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34824 >
2025-06-05 20:27:33 +02:00
57c5419bbd
anv: Support render to aspect other than IMAGE_ASPECT_COLOR_BIT
...
On ANV the vkCmdBeginRendering function was hard coded to use
VK_IMAGE_ASPECT_COLOR_BIT for all color attachments, instead of using
the aspect bit specified when the vkImageView was initialized, which
made it impossible for applications to render to views of multi-planar
formats like VK_FORMAT_G8_B8R8_2PLANE_420_UNORM correctly.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13221
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35340 >
2025-06-05 09:22:16 +00:00
4502254cd2
anv: Drop the slow clear heuristic
...
This no longer provides a performance improvement.
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33776 >
2025-05-13 15:13:05 +00:00
55d788f434
anv/ds: Associate the VkCommandBuffer some anv-only renderstage events.
...
This means the perfetto UI will have a non-zero/NULL handle/name in the UI
on these renderstages. Unfortunately, intel/ds is outside of vulkan so
unless we pull in anv headers, we can't just pass in the anv_cmd_buffer.
This also means it would be much more painful to pass the cmd buffer to
the rest of the events, so they'll still have unset command buffers.
Still, being able to see the name of the command buffer in at least one of
the events should be useful once that's glued together.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22350 >
2025-05-08 01:21:25 +00:00
bb61a78911
anv: Fix untyped data port cache pipe control dump output
...
Fixes: 845ab3d627sagar.ghuge@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34855 >
2025-05-07 19:29:50 +00:00
cf9b0dd589
anv, hasvk: ignore QFOT if both src and dst queue families are equal
...
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34779 >
2025-05-02 17:38:56 +00:00
161c412a82
intel: Fix the MOCS values in XY_FAST_COLOR_BLT for Xe2+
...
Xe2 changed the MOCS field in few instructions, those now have a field
for the MOCS index and other the encryption enable bit but ISL returns
the combination of both aka MEMORY_OBJECT_CONTROL_STATE.
To minimize changes I have added 2 macros to extract the values
from the value returned by isl.
From all the instructions changed Mesa only make use of two, so the
other instruction will be handled in the next patch.
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34592 >
2025-04-22 20:42:25 +00:00
1bf8542490
anv: Enable VK_EXT_external_memory_acquire_unmodified
...
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Change-Id: If0480721f7f1fceec093e4ab7b5c9b712eb62ba1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32295 >
2025-04-21 13:55:32 -07:00
3613b9c4f7
anv: Fix comment about external queue transitions
...
Not all images with DRM format modifiers use
ANV_IMAGE_MEMORY_BINDING_PRIVATE.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Change-Id: Idc6bae70ec7080f96555a85dcdc0ead915b02935
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32295 >
2025-04-21 13:55:27 -07:00
e87a04c6c1
anv: Assert that only external images have private bindings
...
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Change-Id: If2f18d88d48f70a58e236080632e72afb94f5e0b
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32295 >
2025-04-21 13:55:08 -07:00
243c01c703
anv/iris: implement Wa_18040903259
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433 >
2025-04-11 13:54:35 +00:00
d123aedfc7
anv: remove ALWAYS_INLINE from globally visible functions
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433 >
2025-04-11 13:54:35 +00:00
938f79ed82
anv: update Wa_1607156449 to use WA infrastructure
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433 >
2025-04-11 13:54:35 +00:00
7fca7cc721
anv: wire VkAccessFlagBits3KHR flags in internal helpers
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138 >
2025-03-29 02:15:18 +00:00
c6757cb8f0
isl: enable CPB compression
...
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10760
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20741 >
2025-03-28 04:38:09 +00:00
dadd84f5a8
anv: no need to handle transitions for CPB surfaces
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20741 >
2025-03-28 04:38:09 +00:00
32d25075ae
anv: relax depth/stencil<->color copy restrictions
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Ivan Briano <ivan.briano@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31983 >
2025-03-25 08:01:15 +00:00
de2a65ade6
anv: fix non page aligned descriptor bindings on <Gfx12.0
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: ab7641b8dcivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33911 >
2025-03-12 12:23:24 +00:00
d254dc4eaf
anv: move index buffer entry point out of genX code
...
Take the opportunity to move to 64bit address + mocs.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33909 >
2025-03-12 09:37:50 +00:00
888b2ec7b0
anv: break down Wa_16014912113 in need/apply parts
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33751 >
2025-03-05 17:20:12 +00:00
e4f31b8744
intel/ds: rework RT tracepoints
...
That way we can identify single dispatch within each step.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Michael Cheng <michael.cheng@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33684 >
2025-02-24 08:08:02 +00:00
765f3b78d5
anv: apply cache flushes on pipeline select with gfx20
...
This fixes rendering artifacts seen with Hogwarts Legacy and Black
Myth Wukong. Assumption is that we can get rid of these flushes once
RESOURCE_BARRIER work lands but until then we need them.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12540
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12489
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33397 >
2025-02-18 18:04:45 +00:00
d8381415a6
anv: tighten condition for changing barrier layouts
...
Assertion (or attempting the layout change) is causing crash when
launching Steel Rats. Tighten the condition for change so that it should
affect only when runtime has made changes.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12602
Fixes: eed788213btapani.palli@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33523 >
2025-02-18 06:30:14 +00:00
26347b4876
anv: use heap size to program generate state heap
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32895 >
2025-02-05 09:56:03 +00:00
35f02d8f36
anv: Inline can_fast_clear_with_non_zero_color
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31374 >
2025-01-14 03:43:55 +00:00
83cd73385a
anv: Use L3 Fabric flush in fast-clear post-amble on TGL
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Replace the Tile Cache flush with an L3 Fabric flush. According to HSD
1604687438, this should be faster.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31600 >
2025-01-14 03:14:00 +00:00
cec086a074
anv: Reduce fast-clear post-amble synchronization
...
On gfx12+, the pre-amble and post-amble flushes contain the stalls
necessary to ensure the prior operation is complete. Remove the extra
uses of ANV_PIPE_END_OF_PIPE_SYNC_BIT in post-amble flushes. Also do
this for the pre-amble flushes, but this doesn't have any impact. The
flush application function will implicitly add the bit.
For A750, this improves the TWWH3 trace in the performance CI by 0.52%
(n=2).
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31600 >
2025-01-14 03:14:00 +00:00
052d7e1a9c
anv: Slow clear if fast-clear cost is not mitigated
...
Fast-clears require expensive flushes beforehand and afterwards. The
cost of flushes are decreased in a series of back-to-back fast-clears as
no extra fast-clear flushes are required in between them. If the ratio
of a command buffer's recorded back-to-back fast clears over independent
fast-clears falls below 1/2, prevent that command buffer from recording
any further fast-clears.
Averaging two runs of our Factorio trace on an A750 shows a +14.37%
improvement in FPS.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32984 >
2025-01-13 20:42:31 +00:00
Lionel Landwerlin