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anv: store layout_type on the bind_map for convenience

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Pipeline layout is going away.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36512>
This commit is contained in:
Lionel Landwerlin
2025-04-02 17:36:04 +03:00
committed by Marge Bot
parent e52c1c3ba4
commit 8d5cb999f9
7 changed files with 25 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/vulkan/anv_nir.h
-2
View File
@@ -107,7 +107,6 @@ bool anv_nir_lower_ubo_loads(nir_shader *shader);
bool anv_nir_apply_pipeline_layout(nir_shader *shader,
const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags,
enum anv_descriptor_set_layout_type layout_type,
struct anv_descriptor_set_layout * const *set_layouts,
uint32_t set_count,
const uint32_t *dynamic_offset_start,
@@ -123,7 +122,6 @@ bool anv_nir_compute_push_layout(nir_shader *nir,
struct brw_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map,
const struct anv_pipeline_push_map *push_map,
enum anv_descriptor_set_layout_type desc_type,
void *mem_ctx);
void anv_nir_validate_push_layout(const struct anv_physical_device *pdevice,
src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+13 -16
View File
@@ -51,7 +51,6 @@ struct apply_pipeline_layout_state {
struct anv_pipeline_bind_map *bind_map;
enum anv_descriptor_set_layout_type layout_type;
struct anv_descriptor_set_layout * const *set_layouts;
uint32_t set_count;
@@ -567,7 +566,7 @@ build_load_storage_3d_image_depth(nir_builder *b,
{
const struct intel_device_info *devinfo = &state->pdevice->info;
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
return build_load_descriptor_mem(
b, desc_addr,
offsetof(struct anv_storage_image_descriptor, image_depth),
@@ -614,7 +613,7 @@ build_load_desc_address(nir_builder *b, nir_def *set_idx, unsigned set_idx_imm,
anv_load_driver_uniform_indexed(b, 1, desc_surface_offsets, set_idx) :
anv_load_driver_uniform(b, 1, desc_surface_offsets[set_idx_imm]);
desc_offset = nir_iand_imm(b, desc_offset, ANV_DESCRIPTOR_SET_OFFSET_MASK);
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
!state->pdevice->uses_ex_bso) {
nir_def *bindless_base_offset =
anv_load_driver_uniform(b, 1, surfaces_base_offset);
@@ -624,7 +623,7 @@ build_load_desc_address(nir_builder *b, nir_def *set_idx, unsigned set_idx_imm,
b, desc_offset,
nir_load_reloc_const_intel(
b,
state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER ?
state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER ?
BRW_SHADER_RELOC_DESCRIPTORS_BUFFER_ADDR_HIGH :
BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH));
}
@@ -905,7 +904,7 @@ binding_descriptor_offset(const struct apply_pipeline_layout_state *state,
bool sampler)
{
if (sampler &&
state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_DIRECT)
state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_DIRECT)
return bind_layout->descriptor_sampler_offset;
return bind_layout->descriptor_surface_offset;
@@ -917,7 +916,7 @@ binding_descriptor_stride(const struct apply_pipeline_layout_state *state,
bool sampler)
{
if (sampler &&
state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_DIRECT)
state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_DIRECT)
return bind_layout->descriptor_sampler_stride;
return bind_layout->descriptor_surface_stride;
@@ -942,7 +941,7 @@ build_surface_index_for_binding(nir_builder *b,
nir_def *set_offset, *surface_index;
if (is_bindless) {
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
set_offset = nir_imm_int(b, 0xdeaddead);
nir_def *desc_addr =
@@ -1027,7 +1026,7 @@ build_sampler_handle_for_binding(nir_builder *b,
b, BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE +
state->set[set].binding[binding].embedded_sampler_index);
} else if (is_bindless) {
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
set_offset = nir_imm_int(b, 0xdeaddead);
nir_def *desc_addr =
@@ -1240,7 +1239,7 @@ build_buffer_addr_for_res_index(nir_builder *b,
nir_address_format addr_format,
struct apply_pipeline_layout_state *state)
{
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT)
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT)
return build_indirect_buffer_addr_for_res_index(b, desc_type, res_index, addr_format, state);
else
return build_direct_buffer_addr_for_res_index(b, desc_type, res_index, addr_format, state);
@@ -1436,7 +1435,7 @@ try_lower_direct_buffer_intrinsic(nir_builder *b,
* descriptors, we'll use A64 messages. This is handled in the main
* lowering path.
*/
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT &&
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT &&
!descriptor_has_bti(desc, state))
return false;
@@ -1453,7 +1452,7 @@ try_lower_direct_buffer_intrinsic(nir_builder *b,
* descriptor set base address + offset. There is no indirect data to
* fetch.
*/
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT &&
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT &&
bind_layout->type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK &&
!descriptor_has_bti(desc, state))
return false;
@@ -1664,7 +1663,7 @@ lower_get_ssbo_size(nir_builder *b, nir_intrinsic_instr *intrin,
state->pdevice->isl_dev.ss.size);
nir_def *desc_range;
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
/* Load the anv_address_range_descriptor */
desc_range =
build_load_descriptor_mem(b, desc_addr, 0, 4, 32, state);
@@ -1708,7 +1707,7 @@ lower_image_load_intel_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin,
nir_def *desc;
if (state->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
switch (nir_intrinsic_base(intrin)) {
case ISL_SURF_PARAM_BASE_ADDRESSS:
desc = build_load_descriptor_mem(
@@ -2361,7 +2360,7 @@ build_packed_binding_table(struct apply_pipeline_layout_state *state,
} else if (state->set[s].desc_buffer_used) {
map->surface_to_descriptor[map->surface_count] =
(struct anv_pipeline_binding) {
.set = (state->layout_type ==
.set = (state->bind_map->layout_type ==
ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER) ?
ANV_DESCRIPTOR_SET_DESCRIPTORS_BUFFER :
ANV_DESCRIPTOR_SET_DESCRIPTORS,
@@ -2557,7 +2556,6 @@ bool
anv_nir_apply_pipeline_layout(nir_shader *shader,
const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags,
enum anv_descriptor_set_layout_type layout_type,
struct anv_descriptor_set_layout * const *set_layouts,
uint32_t set_count,
const uint32_t *dynamic_offset_start,
@@ -2579,7 +2577,6 @@ anv_nir_apply_pipeline_layout(nir_shader *shader,
.mem_ctx = ralloc_context(NULL),
.pdevice = pdevice,
.bind_map = map,
.layout_type = layout_type,
.set_layouts = set_layouts,
.set_count = set_count,
.dynamic_offset_start = dynamic_offset_start,
src/intel/vulkan/anv_nir_compute_push_layout.c
-1
View File
@@ -35,7 +35,6 @@ anv_nir_compute_push_layout(nir_shader *nir,
struct brw_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map,
const struct anv_pipeline_push_map *push_map,
enum anv_descriptor_set_layout_type desc_type,
void *mem_ctx)
{
const struct brw_compiler *compiler = pdevice->compiler;
src/intel/vulkan/anv_pipeline.c
+4 -4
View File
@@ -297,6 +297,7 @@ anv_stage_allocate_bind_map_tables(struct anv_pipeline *pipeline,
&pipeline->layout));
stage->bind_map = (struct anv_pipeline_bind_map) {
.layout_type = pipeline->layout.type,
.surface_to_descriptor = surface_bindings,
.sampler_to_descriptor = sampler_bindings,
.embedded_sampler_to_binding = embedded_sampler_bindings,
@@ -1062,7 +1063,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
NIR_PASS(_, nir, anv_nir_apply_pipeline_layout,
pdevice, stage->key.base.robust_flags,
layout->type, layout->set_layouts, layout->num_sets,
layout->set_layouts, layout->num_sets,
layout->independent_sets ? NULL : layout->dynamic_offset_start,
&stage->bind_map, &push_map, mem_ctx);
@@ -1130,11 +1131,10 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
pdevice, stage->key.base.robust_flags,
anv_graphics_pipeline_stage_fragment_dynamic(stage),
anv_graphics_pipeline_stage_mesh_dynamic(stage),
prog_data, &stage->bind_map, &push_map,
pipeline->layout.type, mem_ctx);
prog_data, &stage->bind_map, &push_map, mem_ctx);
NIR_PASS(_, nir, anv_nir_lower_resource_intel, pdevice,
pipeline->layout.type);
stage->bind_map.layout_type);
if (gl_shader_stage_uses_workgroup(nir->info.stage)) {
NIR_PASS(_, nir, nir_lower_vars_to_explicit_types,
src/intel/vulkan/anv_pipeline_cache.c
+2
View File
@@ -333,6 +333,7 @@ anv_shader_bin_serialize(struct vk_pipeline_cache_object *object,
sizeof(shader->bind_map.sampler_sha1));
blob_write_bytes(blob, shader->bind_map.push_sha1,
sizeof(shader->bind_map.push_sha1));
blob_write_uint32(blob, shader->bind_map.layout_type);
blob_write_uint32(blob, shader->bind_map.surface_count);
blob_write_uint32(blob, shader->bind_map.sampler_count);
blob_write_uint32(blob, shader->bind_map.embedded_sampler_count);
@@ -397,6 +398,7 @@ anv_shader_bin_deserialize(struct vk_pipeline_cache *cache,
blob_copy_bytes(blob, bind_map.surface_sha1, sizeof(bind_map.surface_sha1));
blob_copy_bytes(blob, bind_map.sampler_sha1, sizeof(bind_map.sampler_sha1));
blob_copy_bytes(blob, bind_map.push_sha1, sizeof(bind_map.push_sha1));
bind_map.layout_type = blob_read_uint32(blob);
bind_map.surface_count = blob_read_uint32(blob);
bind_map.sampler_count = blob_read_uint32(blob);
bind_map.embedded_sampler_count = blob_read_uint32(blob);
src/intel/vulkan/anv_private.h
+3
View File
@@ -4774,6 +4774,9 @@ struct anv_pipeline_bind_map {
unsigned char sampler_sha1[20];
unsigned char push_sha1[20];
/* enum anv_descriptor_set_layout_type */
uint32_t layout_type;
uint32_t surface_count;
uint32_t sampler_count;
uint32_t embedded_sampler_count;
src/intel/vulkan/genX_cmd_buffer.c
+3 -4
View File
@@ -2240,16 +2240,15 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
continue;
}
const struct anv_pipeline *pipeline = pipe_state->pipeline;
uint32_t surface_state_offset;
if (pipeline->layout.type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
if (map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT) {
surface_state_offset =
emit_indirect_descriptor_binding_table_entry(cmd_buffer,
pipe_state,
binding, desc);
} else {
assert(pipeline->layout.type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_DIRECT ||
pipeline->layout.type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER);
assert(map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_DIRECT ||
map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER);
surface_state_offset =
emit_direct_descriptor_binding_table_entry(cmd_buffer, pipe_state,
set, binding, desc);