Commit Graph

11178 Commits

Author SHA1 Message Date
Jordan Justen
c6e855b64b intel/compiler: Verify SIMD16 is used for xe2 BTD/RT dispatch
Ref: HSD 14011192593

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
Jordan Justen
820e04ead4 intel/compiler: Implement nir_intrinsic_load_topology_id_intel for xe2
Rework:
 * Sagar: Rework BRW_TOPOLOGY_ID_DSS, BRW_TOPOLOGY_ID_EU_THREAD_SIMD
   calculations

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
Sagar Ghuge
8f880d0ad7 intel/dev: Update max_subslices_per_slice comment
Mention that max_subslices_per_slice relates to GT_SS_PER_SLICE in SKU.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
Jordan Justen
b533bf7361 intel/compiler: Set branch shader required-width as 16 for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
José Roberto de Souza
4423454daa intel/common: Implement xe_engines_is_guc_semaphore_functional()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
dff96257da intel/common: Implement i915_engines_is_guc_semaphore_functional()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
29ee85c203 anv: Use intel_engines_supported_count()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
fe2982278f intel/common: Add intel_engines_supported_count()
This function is intented to check for KMD, platform or debug options
and return the number of engines that can actually be used.

Next patches will implement i915/xe_engines_is_guc_semaphore_functional()
functions.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
ffca423472 intel: Remove circular dependency between intel/dev and intel/common
intel/common has a build dependency on intel/dev so the later should
not have any dependendies on the first.

So here moving the definition of intel_engine_class to
intel_device_info.h because it is used in intel_device_info struct
and then including intel_device_info.h in intel_engine.h.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
6b5c446556 intel/common: Fix location of C++ support macro in intel_gem.h
'extern "C" {' must be added before any includes otherwise the braces
would not match when 'extern "C" {' is defined in other headers.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
398bdb46ba anv: Drop include to common/i915/intel_gem.h
Common code should not directly include KMD specific files.
At least there was no usage from symbols defined in this file.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
Lionel Landwerlin
e54638ddf5 anv: fix buffer marker cache flush issues on MTL
For some yet unknown reason the CS L3 coherency setting is different
on MTL than DG2.

Fixes issues in tests from the subgroup :

  dEQP-VK.api.buffer_marker.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c8e122a738 ("anv: Implement rudimentary VK_AMD_buffer_marker support")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27613>
2024-02-14 13:45:46 +00:00
Lionel Landwerlin
34078b67ed anv: don't allocate aux padded BOs with host pointers
We can't allocate additional space with host pointers anyway. These
are already allocated pieces of memory by the application.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 646a7c864d ("anv: re-introduce BO CCS allocations")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10608
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27612>
2024-02-14 11:51:33 +00:00
Lionel Landwerlin
feb7cf82dc anv: remove redundant asserts
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27611>
2024-02-14 11:07:10 +00:00
Mark Janes
2143da6d5a intel/dev: improve meson invocation for intel_device_info gen
Review for related code-generation commits advised that the use of an
--outdir parameter was undesirable.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27557>
2024-02-13 19:38:36 +00:00
Mark Janes
f95b87a3dc intel/tools: load json device info in drm_shim
Enable drm_shim to parse a serialized intel_device_info structure from
json.  When overriding the gpu hardware, drm_shim provides the stubbed
intel_device_info structure to mesa through an unused ioctl.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27557>
2024-02-13 19:38:36 +00:00
Mark Janes
56da473b6f intel/dev/tools: add json as an output format for intel_dev_info
intel_dev_info prints out struct intel_device_info in a user-friendly
format.  Json format enables this information to be used as input for
tools.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27557>
2024-02-13 19:38:36 +00:00
Mark Janes
1f725a222a intel/dev: implement json serialization for intel_device_info
Generate intel_device_serialize.c from a mako template, providing
functions to dump and parse intel_device_info.

intel_device_info.py declares python objects representing all type
declarations associated with intel_device_info.  It is used as a data
source for intel_device_serialize_c.py

intel_device_serialize_c.py emits a c++ file with routines to dump
or load all struct members to/from json.  The json format is a direct
translation of the c structure, with 2 exceptions:

 - When parsing json, the no_hw member is always set to true to
   indicate that the driver's intel_device_info does not correspond to
   the current platform.

 - When dumping to json, devinfo_type_sha1 is calculated to be a
   checksum which changes whenever intel_device_info is updated.  This
   checksum is encoded in json.  When parsing json, the driver verifies
   that the checksum matches before loading data into
   intel_device_info.  This verifies compatibility.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27557>
2024-02-13 19:38:36 +00:00
Mark Janes
e56f810316 intel/tools: add intel device meson dependencies
idep_intel_dev ensures that headers are generated before dependent
source files are compiled.  Some tools have been building without that
dependency, and encounter intermittent compilation errors on
sufficiently parallel builds.

Any target which depends on idep_intel_dev will link with
libintel_dev.  Redundant link instructions can be removed.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10604
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27600>
2024-02-13 18:37:19 +00:00
José Roberto de Souza
d0fba810b3 intel: Fix intel_get_mesh_urb_config()
The round up in 'next_address_8kb = DIV_ROUND_UP(push_constant_kb, 8)'
was not decreasing the amount of URB available for Mesh and Task, what
could cause an over allocation of URB.

There was also no minimum entries enforcement for Mesh and Task, what
could cause 0 r.mesh_entries to be set in a case where tue_size_dw is
90% > than mue_size_dw. Same for r.task_entries when Task is enabled.

Also adding a few more asserts to help debug.

This fixes at least dEQP-VK.mesh_shader.ext.properties.mesh_payload_size
in LNL but it has potential to fixes other Mesh tests as well.

Cc: mesa-stable
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27555>
2024-02-13 15:06:32 +00:00
Tapani Pälli
29a6beb36e anv: revert cache flushing changes for indirect commands
This reverts commit d699600da1.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10600
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27591>
2024-02-13 09:47:32 +00:00
Lionel Landwerlin
f192ea630a intel/shaders: enable gfx8 support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
76c3d97c84 intel/shaders: add iris variant of indirect draws generation shader
Iris does not use Gfx11+ SGVS extended parameters, so we have to rely
on the old Gfx9 method of providing the parameters through vertex
buffers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
b52e25d3a8 anv: rewrite internal shaders using OpenCL
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
1e31fd5f42 meson: add option to install intel-clc
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
a26c7b0b03 intel/ds: new tracepoints for generated commands
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
472f49ef43 genxml: remove NDEBUG_UNUSED
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
41b2ed65e2 genxml: generate opencl packing headers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
2a0328ba8b genxml: enable opencl code generation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
e6b5196079 intel-clc: print text input
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
4fd7495c69 intel/clc: add ability to output NIR
This will be used to generate a serialized NIR of functions for
internal shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
2bae1b6b66 intel-clc: move ISA generation to its own function
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
2a1ff08376 intel/compiler: make default NIR compiler options visible
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:45 +00:00
Lionel Landwerlin
c53a4711cb anv: fix incorrect flushing on shader query copy
When doing query result copies in 3D mode, we're flushing the render
target cache, but the shader writes go through the dataport.

Fixes flakes/fails in piglit with shader query copies forced with Zink :

  $ query_copy_with_shader_threshold=0 ./bin/arb_query_buffer_object-coherency -auto -fbo

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b3b12c2c27 ("anv: enable CmdCopyQueryPoolResults to use shader for copies")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:44 +00:00
Lionel Landwerlin
2437556d83 intel/fs: rerun divergence prior to lowering non-uniform interpolate at sample
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 74a40cc4b6 ("intel/fs: move lower of non-uniform at_sample barycentric to NIR")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:44 +00:00
Lionel Landwerlin
8f5a7f57df intel/fs: indent lowering code to make it more readable
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:44 +00:00
Lionel Landwerlin
c517088cf1 anv: factor out post submit queue debug code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:44 +00:00
Lionel Landwerlin
67f3fa896e intel/dev: fix missing dependency on generated packing heaers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797>
2024-02-13 00:06:44 +00:00
Sagar Ghuge
98b62434bd intel/compiler: Lower texture operation to combine LOD and AI
We have to push the lowering of texture operations a bit further in
pipeline since nir_lower_tex gets invoked twice and if there is no LOD
source present, nir_lower_tex adds that as a source. Once that's all
done we can easily combine the LOD and array index into a single 32-bit
value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge
15129c7634 intel/compiler: Use nir_tex_src_backend1 to pack LOD and array index
Since this lowering is totally Intel specific, we don't have to
introduce the new texture source. We can use the nir_tex_src_backend1
source to pack LOD/LOD Bias and array index into 32 bit single value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge
73a3257968 intel/compiler: Add texture operation lowering pass
This pass combines the LOD or LOD bias and array index into a single
32-bit value since Xe2+ sampler messages requires us to do that.

v2: (Alyssa)
- Use nir_iand_imm instead of nir_iand and nir_imm_int
- Use nir_trim_vector instead of nir_swizzle

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Lionel Landwerlin
646a7c864d anv: re-introduce BO CCS allocations
On Gfx12.0, CCS allocations have to be allocated per image because the
format of the image goes into the AUX-TT PTEs. The effect on memory
allocations is limited since the main surface granularity in the
AUX-TT PTE is 64KB.

On Gfx12.5, the granularity of the AUX-TT PTE is 1MB. This creates a
lot of waste in the application memory allocations. Fortunately the HW
doesn't care about the format put into the PTEs anymore. So it becomes
possible to have 2 images share the same PTE.

To implement this we bring back an earlier version of AUX-TT mappings
where we used to allocate additional CCS space at the end of the
VkDeviceMemory objects. On Gfx12.5, if the BO has additional CCS
space, we will now map the main surface to that space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
bd197c6bcf intel/aux_map: add helper to compute offset in aux data
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
c0889a127b intel/aux_map: add BSpec reference
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
da6484a8a4 anv: use address helper to compute address u64 value
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
7763e75eea anv: move ALLOC_HOST_CACHED_COHERENT as define
That way gdb can decode the other flags when looking at the variables.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
3f64ec141e isl: add a no-aux-align usage flag
This flag signals that the driver will be dealing with aux-tt
alignment requirements on its own.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
44515bb92c isl: printout sparse usage
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Sviatoslav Peleshko
28ad2f488a anv: Store host-located copy of NULL surface state for faster memcpy
Real null_surface_state is located in the GPU memory, so copying from
there will be slow for dGPUs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10594
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27577>
2024-02-12 17:48:15 +00:00
Lionel Landwerlin
e0b4dfbbda anv: don't unmap AUX ranges at BO delete
It is possible to free memory backing images before images are
destroyed :

   VkFreeMemory:

   "Memory can be freed whilst still bound to resources, but those
    resources must not be used afterwards."

The spec leaves us the option to keep a reference on the associated
memory and free it only when all the bound resources have been
destroyed. Here we choose to free memory immediately.

One particular test in the CTS
(dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics)
does the following :

   imgA = vkCreateImage()
   imgB = vkCreateImage()
   memA = vkAllocateMemory()
   vkBindImageMemory(imgA, memA) # Aux mapping with ref count = 1
   vkFreeMemory(memA)            # Aux mapping removed, ref count = 0
   memB = vkAllocateMemory()     # Same address as memA
   vkBindImageMemory(imgB, memB)
   vkDestroyImage(imgA)	         # Removes the mapping of imgB-memB

   vkQueueSubmit()               # hang with pagefault in AUX-TT

The solution implemented in this change is to not do anything AUX-TT
related in vkFreeMemory(). This soluation has some consequences,
because a virtual memory address range freed and reallocated cannot be
rebound in the AUX-TT until all the associated resources have released
their AUX-TT mapping (to bring back the AUX-TT refcount of the range
to 0). This should still be better than keeping the memory allocated
through refcounting of the anv_bo.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7b87e1afbc ("anv: track & unbind image aux-tt binding")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10528
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27566>
2024-02-12 15:37:18 +00:00