AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
153,741 Commits 1 Branch 0 Tags
101a7321c4002eec9019f2e25d40d931f74e90b9
Commit Graph

153741 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Timur Kristóf 101a7321c4 radv: Fill task shader info. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
 2022-05-12 00:29:51 +00:00
Timur Kristóf c34aa78496 radv: Set wave size for task shaders. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
 2022-05-12 00:29:51 +00:00
Timur Kristóf 988600e522 radv: Set user data register for task shaders. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
 2022-05-12 00:29:51 +00:00
Timur Kristóf bb71d1092b radv: Add radv_pipeline_has_task helper. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
 2022-05-12 00:29:51 +00:00
Timur Kristóf 285d20d3c5 ac: Add task ring entry shader argument. 
This is going to be used by both task and mesh shaders for
accessing the draw and payload ring buffers.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
 2022-05-12 00:29:51 +00:00
Timur Kristóf 7de3034897 ac/nir: Add I/O lowering for task and mesh shaders. 
Task shaders store their output payload to VRAM where mesh
shaders read from. There are two ring buffers:

1. Draw ring: this is where mesh dispatch sizes and
the ready bit are stored.

2. Payload ring: this is where the optional payload
is stored (up to 16K per task workgroup).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
 2022-05-12 00:29:51 +00:00
Jason Ekstrand df1876f615 nir: Mark negative re-distribution on fadd as imprecise 
Otherwise, it would mutate `fneg(fadd(-0, 0))` into `fadd(0, -0)` which
isn't correct since -0 + (+0) = +0 + (-0) = +0.

This fixes the OpenCL contraction tests on Iris.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16041>
 2022-05-12 00:05:10 +00:00
Jason Ekstrand 62f0677223 iris: Set BindingTableEntryCount for compute shaders 
This may slightly increase perf somewhere because the hardware can now
pre-cache binding tables.  The real feature is that INTEL_DEBUG=bat now
dumps out surface states for compute.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15759>
 2022-05-11 23:47:08 +00:00
Charmaine Lee 55a4bdb52f svga: workaround for unexpected double swizzle 
SM5 requires swizzles for 64 bits alu source to be either .xyzw,
.xyxy, .zwxy, or .zwzw. If the swizzles are not in the valid pattern,
move the source according to the specified swizzle to a temporary register
first.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16464>
 2022-05-11 23:14:03 +00:00
Alyssa Rosenzweig 5cfae66cde pan/bi: Ensure the end NOP isn't eliminated 
Otherwise the lowering doesn't work.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Alyssa Rosenzweig 6d41a28a40 pan/bi: Support atomics on Valhall 
Atomics on Valhall work basically the same as on Bifrost, however the
instruction selection is simplified as there are no clauses. Support the
simplified set of atomic instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Alyssa Rosenzweig 21900ec8b0 pan/bi: Handle shared/scratch on Valhall 
There's no .seg modifier, so we have some easy lowering to do ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Alyssa Rosenzweig b683a67328 pan/bi: Handle shared atomic exchange on Valhall 
Need to lower the WLS into a segment addition, since the .seg modifier was
dropped on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Alyssa Rosenzweig 6e2b757bce pan/bi: Preserve AXCHG.i32 destination 
dEQP-GLES31.functional.image_load_store.2d.atomic.exchange_r32f_result

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Alyssa Rosenzweig 20f92871d8 pan/bi: Support image loads on Valhall 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Alyssa Rosenzweig e53f44a4b8 pan/bi: Emit LEA_TEX on Valhall 
As opposed to LEA_ATTR_TEX. In principle we could do this for Bifrost too, but
let's keep the Midgard compatible path for now.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Alyssa Rosenzweig 423773faa9 pan/bi: Don't analyze td on Valhall 
The implementation is based on clauses, so it won't work on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>
 2022-05-11 21:57:13 +00:00
Autumn on Tape d561279c7b lavapipe: enable subgroup quad operations 
Signed-off-by: Autumn on Tape <autumn@cyfox.net>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16340>
 2022-05-11 21:09:43 +00:00
Corentin Noël 2e3cf3a6a6 mesa: Make sure to fallback to handling the original choose texture format 
It is possible for st_ChooseTextureFormat to return MESA_FORMAT_NONE when
samples is forced to 2. Always allow to fallback to the original case.

Fixes: 89c94502b6
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6441
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16432>
 2022-05-11 19:55:34 +00:00
Dave Airlie 24176cae55 aco: drop unused radv include 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie c44d5d61ce aco: remove radv vs prolog key from aco internals. 
This creates an aco specific key, and converts radv to it.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie 04c07a2413 aco/radv: convert to aco shader info at the radv level. 
This removes the radv shader info type from aco completely.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie 199edce84d aco/info: add some more fields. 
These fields are also used in aco.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie 8cfd8420ab aco: convert vs and so info over to aco structs. 
This renames the vs to vp (vertex pipeline) on the way past.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie 3dba3458e9 aco: remove radv specific streamout info 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie 9bd89af1bc aco/info: reduce the gs ring info to what is needed. 
Only one member was being used.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie 87df607ff5 aco: move to a minimal aco shader info struct. 
This should be kept to only things aco uses, and expanded when
radeonsi support is added. Things should be removed if lowered in NIR.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Dave Airlie a2701bfdb8 aco: move info pointer to a copy. 
This is just setup to move this to a different struct later.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>
 2022-05-11 19:07:11 +00:00
Georg Lehmann 29fbc88d6b radv: Don't retile read-only images. 
Avoid unnessecary work on FOREIGN queue release barriers. If we can't modify
the image there can't be a situation where we need to update the presentable
dcc data.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16371>
 2022-05-11 18:43:11 +00:00
Danylo Piliaiev 6bf4ae002a pps: Open writable renderer node in DrmDevice::create 
DrmDevice::create_all correctly opened the node with O_RDWR, while
DrmDevice::create was not, causing failure to create writable buffer.

Fixes pps-config on Freedreno.

Fixes: 1cc72b2aef
("pps: Gfx-pps v0.3.0")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16406>
 2022-05-11 15:41:28 +00:00
Jason Ekstrand e4ad1b5b33 panvk: Advertise support for logicOp 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand 25249e8be2 nir/lower_blend: Expand or shrink output variables as needed 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand 7aec8db161 midgard: Handle FB fetch from non-vec4 output variables. 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand 1d22465362 nir/builder: Add a nir_resize_vector helper 
We're about to use this a couple of places.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand 352e32e5ba nir/builder: Add a nir_trim_vector helper 
This pattern pops up a bunch and the semantics of nir_channels() aren't
very convenient much of the time.  Let's add a nir_trim_vector() which
matches nir_pad_vector().

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand 244b654de6 nir/lower_blend: Support SNORM and integer formats for logic ops 
This fixes 158 of the dEQP-VK.pipeline.logic_op.* tests, once we turn
the feature on.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand 730d2b7660 nir/lower_blend: Stop passing the whole options object around 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand dcfffdcad1 nir/lower_blend: Be more explicit about deref assumptions 
Because we pull the RT from the variable location and use that to look
up formats, we need a constant RT index.  To deal with arrays (possibly
of arrays), we would either need to handle array derefs (we don't today)
or we need to require the variables to be split into one variable per
RT.  Given that we have to lower indirect derefs anyway (to get constant
indices), we may as well require the client to split output variables by
calling nir_lower_io_arrays_to_elements_no_indirect().

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Jason Ekstrand 885437d1a6 panvk: Call nir_lower_io_arrays_to_elements_no_indirects 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00
Martin Roukala (né Peres) ac0a61e17b ci/radv: remove amdgpu.gpu_recovery=0 from the kernel cmdline 
This was set as an attempt to detect when the GPU got hung, and let
our hangcheck detect this issue and kill the run. This however has
not been working so well, so let's try without it.

Suggested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16423>
 2022-05-11 10:25:06 +00:00
Iago Toral Quiroga c708da6e29 v3dv: expose VK_KHR_spirv_1_4 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16424>
 2022-05-11 09:12:27 +00:00
Iago Toral Quiroga e981ed21e3 v3dv: expose VK_KHR_shader_float_controls 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16424>
 2022-05-11 09:12:27 +00:00
Danylo Piliaiev 187d3df52c tu: Do not flush ccu in clear/blits during renderpass 
For clear/blits ccu flush not only worse for perf, but also messes up
flush_bits when executed in a conditional set of commands.

We already don't flush for 3d blits.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6419

Fixes: 487aa807bd
("tu: Rewrite flushing to use barriers")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16352>
 2022-05-11 08:07:50 +00:00
Samuel Pitoiset 66888d5121 radv: remove useless check against nir_texop_samples_identical 
nir_texop_samples_identical is lowered to
nir_texop_fragment_mask_fetch_amd earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16426>
 2022-05-11 06:55:21 +00:00
Marek Olšák 98ea2347a0 radeonsi: report more missing/broken texture formats as unsupported on gfx6-9 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16386>
 2022-05-11 06:21:11 +00:00
Marek Olšák e4283708f0 radeonsi: report 10_10_10_2 scaled formats as unsupported on gfx6-9 as well 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16386>
 2022-05-11 06:21:11 +00:00
Dave Airlie 9775da1196 radv: optimised command buffer reset of vertex bindings. 
This takes the buffer ptrs out of the struct, so they can be memset
separately and optimises the memset to be minimal for them.

Removing them from the struct avoids having to loop to clear them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>
 2022-05-11 05:19:38 +00:00
Dave Airlie 543d52a7a2 radv: only dirty line stipple when necessary. 
Line stipple only cares if things changes to/from line strip.

Reduces overheads seen running pixmark volplosion with zink.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>
 2022-05-11 05:19:38 +00:00
Dave Airlie b20bd9e0df radv: cache the slab bo pointer in the pipeline. 
Otherwise each emission has to pointer chase across cachelines.

Reduces overhead seen with zink on pixmark volplosion test.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>
 2022-05-11 05:19:38 +00:00
Dave Airlie 87f4252a51 zink: don't finish barriers cmd buffer if not used. 
finishing has some cpu overhead, which if the cmd buffer isn't
going to be used is pointless. just let it get reset next time.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>
 2022-05-11 05:19:38 +00:00