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Author SHA1 Message Date
Thong Thai
0f8ef37f65 radeon/vcn: fix jpeg decode for navi10 
Fixes an issue where the JPEG decode would timeout when decoding certain JPEG files.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6249>
 2020-08-10 16:39:48 +00:00
Bas Nieuwenhuizen
e362ccb20c radv: Do not consider layouts fast-clearable on compute queue. 
We cannot decompress from the compute queue. While I'm pretty sure
VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL is only useful on the
graphics queue, I cannot find a VU that prevents the transition
from happening on another queue, so we need to be careful here.

This patch ensures we do the decompression on the barrier that changes
the queue ownership.

Another problem was that DCC images were considered fast-clearable
when not DCC compressed, which resulted in a mess with concurrent
queue ownership.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3387
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6252>
 2020-08-10 16:24:38 +00:00
Bas Nieuwenhuizen
2fa83dc64d radv: Add forcecompress debug flag. 
Enables DCC/HTILE/CMASK/FMASK when supported, not just when we think
it is beneficial.

This is helpful to detect compression bugs with CTS.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6252>
 2020-08-10 16:24:38 +00:00
Marcin Ślusarz
a777b25350 intel/perf: export performance counters sorted by [group|set] and name 
It's a lot easier to deal with them in RenderDoc when they are
in some meaningful order.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5788>
 2020-08-10 13:41:29 +00:00
Marcin Ślusarz
59716e40b0 intel/perf: split load_oa_metrics 
Move oa_metrics_available out of load_oa_metrics and call
build_unique_counter_list outside.

This change is a preparation for the next patch. It should
not have any functional impact.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5788>
 2020-08-10 13:41:29 +00:00
Marcin Ślusarz
2fbab5a1b3 intel/perf: fix performance counters availability after glFinish 
Currently Linux kernel gathers performance counters at fixed
intervals (~5-10ms), so if application uses AMD_performance_monitor
extension and immediately after glFinish() asks GL driver for HW
performance counter values it might not get any data (values == 0).

Fix this by moving the "read counters from kernel" code from
"is query ready" to "get counter values" callback with a loop around
it. Unfortunately it means that the "read counters from kernel"
code can spin for up to 10ms.

Ideally kernel should gather performance counters whenever we ask
it for counter values, but for now we have deal with what we have.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5788>
 2020-08-10 13:41:29 +00:00
Marcin Ślusarz
9fa64803aa intel/perf: streamline error handling in read_oa_samples_until 
No functional changes.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5788>
 2020-08-10 13:41:29 +00:00
Marcin Ślusarz
03e8b3551c intel/perf: fix how pipeline stats are stored 
It matters only when counters are not ordered by offset.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5788>
 2020-08-10 13:41:29 +00:00
Marcin Ślusarz
e7e6f70938 intel/perf: fix calculation of used counter space 
It matters only when counters are not ordered by offset.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5788>
 2020-08-10 13:41:29 +00:00
Samuel Pitoiset
6d988ad4a2 radv: report a better error message when QueueWaitIdle() failed 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6230>
 2020-08-10 14:09:23 +02:00
Samuel Pitoiset
3691ef5596 radv: report errors back to the application via VK_EXT_debug_report 
Help for debugging.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6230>
 2020-08-10 14:09:21 +02:00
Samuel Pitoiset
cc4b9c2128 radv: rework the error function helpers a bit 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6230>
 2020-08-10 14:09:19 +02:00
Samuel Pitoiset
11781c0e49 radv: report the spirv-nir logs back to the application 
Via VK_EXT_debug_report to help debugging various SPIRV->NIR issues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6223>
 2020-08-10 13:19:21 +02:00
Bas Nieuwenhuizen
ff4f6202be radv: Fix assert that is too strict. 
The added assert fails on MSAA images if we disable FMASK ....

Reordered things.

Fixes: c6aadbae71 "radv: Don't use both DCC and CMASK for single sample images."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3385
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6232>
 2020-08-10 09:34:49 +00:00
Louis Li
f7e7cf637e radeon/radeon_vce: fix out of target bitrate in CBR mode (H.264) 
StoneyRidge may not comply to required target bitrate
when generating H.264 stream in CBR mode.

Signed-off-by: Louis Li <Ching-shih.Li@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4384>
 2020-08-10 01:39:18 +00:00
Gert Wollny
4975b3ec55 r600: Enable compute shaders for NIR code path 
There are still regessions compared to TGSI, but there are also many
fixes.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:36 +00:00
Gert Wollny
834a61df4e r600/sfn: Force a minimum of 4 GPRs, it seems to fix atomics 
This fixes spec@arb_compute_shader@execution@atomic-counter on
HD 5450

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:36 +00:00
Gert Wollny
3e3068a76a r600/sfn: handle querying SSBO size 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:35 +00:00
Gert Wollny
ac87cc2205 r600/sfn: Correct ssbo instruction handling 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:35 +00:00
Gert Wollny
11a861c78a r600/sfn: correct allocating and emitting of atomics 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:34 +00:00
Gert Wollny
702619c412 r600/sfn: Add a mapping table for atomics 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:34 +00:00
Gert Wollny
56dedf052f r600/sfn: add r600 specific lowering pass for atomics and use it 
v2: rebase to use global variable lists

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:34 +00:00
Gert Wollny
df2acf8e26 r600/sfn: Sort uniforms by binding and offset 
This is required to get atomics right.

v2: rebase to use global variable lists

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:33 +00:00
Gert Wollny
a828f6c513 r600: Set PIPE_CAP_NIR_ATOMICS_AS_DEREF to true 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:33 +00:00
Gert Wollny
a03e24aa7f gallium + mesa/st: Add PIPE_CAP_NIR_ATOMICS_AS_DEREF and use it 
This cap is useful for drivers that support hardware atomics and need
special handling to resolve their addresses.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6025>
 2020-08-09 13:45:32 +00:00
Eric Engestrom
dd003abd2f meson: bump required glvnd version 
https://github.com/KhronosGroup/EGL-Registry/pull/95 has moved
a couple of extensions defines and functions to the upstream `eglext.h`,
but when 9a74746bd1 sync'ed these files we broke compilation
of apps that require these symbols on systems that don't have the
updated Khronos headers.

On non-GLVND builds, we still provide these headers, so everything's
fine, but on GLVND builds the Khronos headers are external so we need to
make sure we have a libglvnd version that's recent enough.

Fixes: 9a74746bd1 ("EGL: sync headers with Khronos")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6069>
 2020-08-08 17:15:25 +02:00
Eric Engestrom
7fbadfc385 driconf: fix force_gl_vendor description 
The option is not a toggle to "allow GPU vendor to be overridden", it
*is* the override.

Fixes: dca119f12c ("mesa/gallium: add dric option to allow overriding GL vendor string")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6207>
 2020-08-08 14:26:08 +00:00
Eric Engestrom
800816d70b egl/entrypoint-check: add check that GLVND and plain EGL have the same entrypoints 
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4448>
 2020-08-08 13:45:06 +00:00
Eric Engestrom
351d513e30 egl/entrypoint-check: split sort-check into a function 
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4448>
 2020-08-08 13:45:06 +00:00
Felix Yan
04bd58ff79 Correct a typo in threads_win32.h 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6238>
 2020-08-08 12:55:33 +00:00
Eric Engestrom
e3069c4257 pick-ui: specify git commands in "resolve cherry pick" message 
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6134>
 2020-08-08 12:27:48 +00:00
Joshua Ashton
b238d17a02 zink: Fix 32-bit compilation 
`sizeof(void*) != sizeof(VkShaderModule)` on x86 hence this fails with `-Werror=int-conversion`

Fixes: 0f059d550b "zink: split up creating zink_shader objects and VkShaderModule objects"

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6239>
 2020-08-08 12:46:51 +01:00
Timothy Arceri
08f3dcf2f6 i965: add support for force_gl_vendor 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3363
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6198>
 2020-08-08 01:05:53 +00:00
Rob Clark
ab92c11780 freedreno/ir3: don't install ir3_compiler cmdline tool 
It is mostly just useful to us.. and it is big since it links in nir and
most of the rest of gallium.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6234>
 2020-08-07 23:20:38 +00:00
Rob Clark
3b6e8670f8 freedreno/registers: add some missing regs to build 
Needed for installed version of crashdec/cffdump.

Fixes: 9c33c53898 ("freedreno/registers: install gzip'd register database")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6234>
 2020-08-07 23:20:38 +00:00
Dylan Baker
1e28745bc0 meson/freedreno: Fix lua requirement 
Freedreno needs at least Lua 5.2, but the current code will report found
for 5.1, which doesn't actually work.

Fixes: caa107cb8d
       ("freedreno/decode: move dependencies up a level")

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6229>
 2020-08-07 17:27:00 +00:00
Marek Olšák
0cdd411b6d radeonsi: various fixes for gfx10.3 
The magic numbers fix sample shading.
The bypass flag is optional.

Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:22 -04:00
Marek Olšák
e2e700f605 radeonsi: remove the NGG hack decreasing LDS usage to deal with overflows 
The LDS size can't overflow anymore, so we can use the correct max LDS size.

Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:22 -04:00
Marek Olšák
97456e847e radeonsi: add a common function for getting the size of gs_ngg_scratch 
The next commit will use it.

Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:22 -04:00
Marek Olšák
68b3e92fef radeonsi: don't count unusable vertices to the NGG LDS size 
Now we get optimal LDS usage.

Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:22 -04:00
Marek Olšák
64c741ffb7 radeonsi: fix applying the NGG minimum vertex count requirement 
The code applied the restriction too late, which could overflow LDS size,
which started happening more often after the minimum vertex count was
increased for Sienna.

Incorporate the clamping into the previous code for rounding up the counts.
Now the LDS size can never overflow, but it may use vector lanes less
efficiently (max_gsprims can be decreased more), which will be addressed
in the next commit.

Fixes: 4ecc39e1aa ("radeonsi/gfx10: NGG geometry shader PM4 and upload")

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák
7a468fc0f6 radeonsi: increase minimum NGG vertex count requirement per workgroup on gfx 10.3 
Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák
633d2aa915 radeonsi: use the same units for esgs_ring_size and ngg_emit_size 
for consistency

Fixes: a23802bcb9 - ac,radeonsi: start adding support for gfx10.3

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák
b6fb09fd84 radeonsi: use correct wave size in gfx10_ngg_calculate_subgroup_info 
Fixes: 88efb63caf ("radeonsi/gfx10: implement Wave32")

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák
61c671c97e Revert "radeonsi: honor a user-specified pitch on gfx10.3" 
This reverts commit c4b5fd9ab0.

It breaks mipmapping. This is only meant to be used by OpenCL, which allows
setting a user pitch for linear images. In all other cases, don't support
a custom pitch.

Fixes: c4b5fd9ab0 "radeonsi: honor a user-specified pitch on gfx10.3"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák
15bd3f3712 ac/gpu_info: set num_tiles_pipes on gfx10+ too 
Based on PAL.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6137>
 2020-08-07 11:22:21 -04:00
Marek Olšák
9333a8570d radeonsi: enable ETC2 hw acceleration on Raven2 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6213>
 2020-08-07 11:04:05 -04:00
Antonio Caggiano
1185b3f32d zink: pre-hash gfx-pipeline-state 
Store a hash in `zink_gfx_pipeline_state` to keep track of state
changes and avoid to recompute it when the state has not changed.

Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6061>
 2020-08-07 15:57:59 +02:00
Mike Blumenkrantz
7be12df5e6 zink: rename zink_gfx_program::stages to 'modules' 
we've been confusing 'stages' and 'shaders' over and over for a long time,
so maybe having a totally different name will help here

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5970>
 2020-08-07 12:36:59 +00:00
Mike Blumenkrantz
6196f2aa93 zink: always compile shaders in pipeline order 
in order to accurately perform slot/location mapping that's consistent across
stages, we need to go through the stages in order so that we can pass each successive
slot map allocation along to the next compiled stage

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5970>
 2020-08-07 12:36:59 +00:00