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10573 Commits

Author SHA1 Message Date
Eric Anholt d4e56930c2 intel/perf: Fix unused var warning in release builds. 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5829>
 2020-07-17 17:44:17 +00:00
Eric Anholt afe07c7fa7 intel: Fix release-build warnings about sf_entry_size. 
In one side of the ifdef it's only used in an assert.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5829>
 2020-07-17 17:44:17 +00:00
Anuj Phogat 559b26b7ee intel/ehl: Add new PCI-IDs 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
 2020-07-14 21:10:04 -07:00
Anuj Phogat 7cb2ace465 intel/ehl: Rename gen_device_info struct 
Renaming makes it easier to relate a pciid with device configuration.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
 2020-07-14 21:10:04 -07:00
Anuj Phogat 13c70931f5 intel/ehl: Use macro GEN11_LP_FEATURES in device info 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
 2020-07-14 21:10:04 -07:00
Anuj Phogat e08ec89a19 intel/ehl: Use GEN11_URB_MIN_MAX_ENTRIES in device info 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
 2020-07-14 21:10:04 -07:00
Eric Engestrom f95637f01a meson: fix android vulkan build 
Android doesn't have `pthread_cancel()` and is unlikely to ever
implement it [1], but `wsi_common_display.c` needs it (or an
alternative).

Let's just disable the platform on Android (as it used to be
before 448eb19158).

[1] https://android-review.googlesource.com/c/platform/bionic/+/1215779/1/docs/status.md

Fixes: 448eb19158 ("vulkan: automatically compile the `display` platform when available")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5860>
 2020-07-14 09:34:54 +00:00
Eric Engestrom b7b72681bd meson/intel: add missing dep on git_sha1.h 
Fixes: 805b32cab9 ("intel: add identifier for debug purposes")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylanx.c.baker@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5882>
 2020-07-13 21:26:25 +00:00
Yevhenii Kolesnikov 36abb0c691 intel/compiler: don't propagate cmp to add if add is saturated 
From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags":

   * Note that the [post condition signal] bits generated at
     the output of a compute are before the .sat.

Paragraph about post_zero does not mention saturation, but
testing it on actual GPUs shows that conditional modifiers
are applied after saturation.

   * post_zero bit: This bit reflects whether the final
     result is zero after all the clamping, normalizing,
     or format conversion logic.

For signed types we don't care about saturation: it won't
change the result of conditional modifier.

For floating and unsigned types there two special cases,
when we can remove inst even if scan_inst is saturated: G
and LE. Since conditional modifiers are just comparations
against zero, saturating positive values to the upper
limit never changes the result of comparation.

For negative values:
(sat(x) >  0) == (x >  0) --- false
(sat(x) <= 0) == (x <= 0) --- true

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2610

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4167>
 2020-07-11 00:25:48 +00:00
Lionel Landwerlin 40a6de176d anv: fix uninitialized variable access 
Found with valgrind :

  ==415016== Conditional jump or move depends on uninitialised value(s)
  ==415016==    at 0x513C22B: anv_cache_lock (anv_pipeline_cache.c:346)
  ==415016==    by 0x513C2A0: anv_pipeline_cache_search (anv_pipeline_cache.c:364)
  ==415016==    by 0x50E7C88: lookup_blorp_shader (anv_blorp.c:38)
  ==415016==    by 0x5D20A98: blorp_params_get_clear_kernel (blorp_clear.c:60)
  ==415016==    by 0x5D23EFD: blorp_ccs_ambiguate (blorp_clear.c:1358)
  ==415016==    by 0x50EDE25: anv_image_ccs_op (anv_blorp.c:1882)
  ==415016==    by 0x555D92F: transition_color_buffer (genX_cmd_buffer.c:1179)
  ==415016==    by 0x5598B71: cmd_buffer_begin_subpass (genX_cmd_buffer.c:5060)
  ==415016==    by 0x559AB00: gen9_CmdBeginRenderPass (genX_cmd_buffer.c:5772)
  ==415016==    by 0x11DACE: begin_render_pass (vr-test.c:375)
  ==415016==    by 0x11DF55: set_state (vr-test.c:529)
  ==415016==    by 0x11F7A1: clear (vr-test.c:1228)

v2: Don't break external sync feature

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5823>
 2020-07-10 17:54:35 +00:00
Eric Engestrom 448eb19158 vulkan: automatically compile the display platform when available 
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3161>
 2020-07-10 13:48:24 +00:00
Jordan Justen 8dfa072ed8 intel/compiler/fs: Still attempt simd32 when INTEL_DEBUG=no16 is used 
If INTEL_DEBUG=no16 is used, then simd16 will not be attempted. This,
in turn prevents simd32 from running, because we attempt to skip
simd32 when simd16 fails to compile.

This change more accurately recognizes when we attempted simd16, but
simd16 failed.

One easy way to cause an issue is to set both no8 and no16. Before
this change, we would be left with no FS program, even though simd32
could still be generated in some cases.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5269>
 2020-07-09 15:44:57 -07:00
Jordan Justen 1a4a2f563b intel/compiler/cs: Allow simd32 in some more cases with no8 and/or no16 
If no16 was specified, and the shader can't run in simd8 due to the
local_size, then we need to generate a simd32 program.

If both no8 and no16 are specified, then we need to generate a simd32
program.

Rework:
 * Drop update of `if` that would have changed `do32` to try simd32
   even if simd16 spilled registers. (Caio)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5269>
 2020-07-09 15:44:34 -07:00
Jason Ekstrand 1d5e1882f6 anv: Handle clamping of inverted depth ranges 
Tested-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5792>
 2020-07-07 21:38:03 +00:00
Lionel Landwerlin edc8119da4 anv: garbage collect timeline semaphore when querying value 
If we don't garbage collect the timeline, the value never progresses
even though work completed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3226
Fixes: 34f32a6d66 ("anv: implement VK_KHR_timeline_semaphore")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5774>
 2020-07-06 22:33:46 +00:00
Marcin Ślusarz 3144bc1d33 intel/perf: move query_mask and location out of gen_perf_query_counter 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5399>
 2020-07-06 21:43:59 +00:00
Marcin Ślusarz 9f19662550 iris: remove iris_monitor_config 
perf_cfg is enough - it already contains almost all necessary
information and is constructed in a more optimal way (O(n) vs O(n^2)
- it uses hash table to build the unique counter list).

"Almost all", because it doesn't contain OA raw counters, but
we should have not exposed them anyway. Quoting Mark Janes:
"I see no reason to include the OA raw counters in the list that
are provided to the user. They are unusable.
The MDAPI library can be used to configure raw counters in a way
that provides esoteric metrics, but that library is written against
INTEL_performance_query."

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5399>
 2020-07-06 21:43:59 +00:00
Timothy Arceri 1a8f918050 intel/compiler: add and fix up fallthrough comments for gcc warnings 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5714>
 2020-07-02 12:11:30 +10:00
Timothy Arceri 512db7ec78 anv: update fallthrough comment so gcc sees it 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5714>
 2020-07-02 12:11:30 +10:00
Matt Turner 8da810a7fb intel/compiler: Don't emit no-op cr0 changes 
If mask is 0, we're asking for no changes to cr0.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5566>
 2020-07-02 01:24:06 +00:00
Matt Turner fe14dc98bf intel/compiler: Add assert that set bits are within mask 
We generate bitfields of bits that we want to retain (mask) and bits
that we want to set (brw_mode) in the cr0 register, so the bits we want
to set should be in the set of bits we want to retain.

Also, remove the initialization of mask from
fs_visitor::emit_shader_float_controls_execution_mode since
brw_rnd_mode_from_nir initializes the mask parameter unconditionally.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5566>
 2020-07-02 01:24:06 +00:00
Jan Beich 2e5b214506 anv: disable i915_perf warning on non-Linux 
$ vkcube
INTEL-MESA: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5461>
 2020-06-30 21:05:52 +00:00
Rafael Antognolli 66df2ffa36 anv: Align "used" attribute to 64 bits. 
This is a 64 bits value that might not be aligned on 32 bit plaforms.
Since it's used with atomics, let's make sure it gets properly aligned
to avoid any potential performance loss.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>
 2020-06-25 22:11:36 -07:00
Kenneth Graunke 8278a46b26 intel: Disable loading drivers on DG1 devices for now 
Kernel support for DG1 has not yet been merged upstream; per our
long-standing DRM subsystem policy, we should not enable the platform
in userspace until the kernel patches are merged and functional.

We will re-enable this in the future.  In the meantime, we retain all
of the infrastructure and code for the platform so that we can continue
developing DG1 support in upstream.

See a discussion here:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956#note_547775

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5617>
 2020-06-24 02:48:04 +00:00
Jordan Justen ecf3335eef anv/cmd_buffer: Split GPGPU_WALKER out to emit_gpgpu_walker 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5571>
 2020-06-24 00:14:36 +00:00
Jordan Justen 759b7f83dd anv/pipeline: Split VFE/INTERFACE_DESCRIPTOR out to emit_media_cs_state 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5571>
 2020-06-24 00:14:35 +00:00
Jason Ekstrand 561aaeeb48 intel/eu: Add the RNDU opcode 
We don't want to use it on gen5 and earlier because only RNDD can be
done with a single instruction and we can implement RNDU(x) as -RNDD(-x)
so it's better to just do that when we have the instruction.  On gen6
and above, we may as well just use the right instruction.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:54 +00:00
Jason Ekstrand e0ab48e3ea intel/eu: Set the right subnr for ALIGN16 destinations 
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:54 +00:00
Jason Ekstrand 8a0d772dca intel/eu: Add a brw_urb_dest_msg_type helper 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:54 +00:00
Kenneth Graunke 2c762955d4 intel/eu: Add a brw_urb_desc helper 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand ecda98fbb2 intel/compiler: Expose brw_texture_offset to C 
Some day we probably want to move it out of brw_shader if we're going to
share it with IBC but that can be another day.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand 479797e130 intel/fs: Move more prog_data setup into populate_wm_prog_data 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand fc519cad57 intel/fs: Break wm_prog_data setup into a helper 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand 2687ec5ee6 intel/fs: Expose a couple of NIR lowering helpers 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5596>
 2020-06-23 17:43:53 +00:00
Jason Ekstrand 6ac99b9f39 anv: Bump the advertised patch version to 145 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5597>
 2020-06-22 23:24:25 +00:00
Jordan Justen c72832e83c anv: Make use of devinfo has_aux_map field 
Reworks:
 * Use device rather than physical_device for info. (Lionel)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572>
 2020-06-22 22:32:03 +00:00
Eric Engestrom 04e8eaf4e8 util: rename xmlpool.h to driconf.h 
To make it clearer what it is and does.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
 2020-06-22 21:50:12 +00:00
Eric Engestrom 2ef983dca6 driconf: drop now unused translation facility 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
 2020-06-22 21:50:12 +00:00
Jordan Justen c323e0ddf3 intel/dev: Add device info for DG1 
Reworks:
 * Anuj: Set is_dg1
 * Anuj: Add dg1 to gen_device_name_to_pci_device_id
 * Anuj: Update simulator id
 * Rafael: has_llc = false

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli 37a724e4ae anv/dg1: Don't use SET_TILING kernel uapi. 
It is not available on discrete platforms anymore.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli 762e601f77 intel/devinfo: Add function to check for DRM_I915_GEM_GET_TILING. 
Future (discrete) platforms won't have support for get/set tiling. This
function allows our drivers to query for that, by simply trying to get
the tiling from a dummy buffer.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli 86617c08cc intel/l3: Return the URB size from devinfo for DG1 
We don't have any URB size set in the L3 config, since it's a fixed
value now. So just return the value that we know from gen_device_info.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Rafael Antognolli 793b409241 intel/isl: Update mocs for DG1 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:42:00 -07:00
Anuj Phogat 3daa866751 intel/l3: Add DG1 L3 configuration 
Reworks:
 * Jordan: Make DG1 L3 config table empty

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Jordan Justen 633dec7163 anv: Set L3 full way allocation at context init if L3 cfg is NULL 
If the platform's default L3 config is NULL, then it now gets
initialized only at context init time, and cmd_buffer_config_l3 will
always return immediately.

Rework:
 * Remove unneeded check on !cfg in cmd_buffer_config_l3 (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Jordan Justen 6054b24f58 intel/l3: Allow platforms to have no l3 configurations 
On some gen12 platforms we will use the L3FullWayAllocationEnable and
never reconfigure the L3 setup.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Jordan Justen 49fe43e15f intel/l3: Don't rely on cfg entry URB size being 0 as a sentinal 
An example entry with URB size being 0 is in the cnl list.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:59 -07:00
Anuj Phogat f1fba99695 intel/devinfo: Add is_dg1 to device info 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
 2020-06-22 11:41:55 -07:00
Arcady Goldmints-Orlov 04f77595f0 intel/compiler: Always apply sample mask on Vulkan. 
With OpenGL, shader writes to the sample mask are ignored when not
rendering to a multisample render target. However, on Vulkan, writes to
the sample mask have still have their effect in that case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3016

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5156>
 2020-06-19 20:24:11 -05:00
Nanley Chery b25fedeff9 isl/drm: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS 
Add an entry for this modifier in the modifier_info array.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
 2020-06-19 23:32:29 +00:00