Commit Graph

10573 Commits

Author SHA1 Message Date
Lionel Landwerlin 16763e8b8e anv: force primitive shading rate write in last geometry stage
v2: Use new helper to check if stage supports variable shading rate
    setting

v3: Update comment & iterate backward (Caio)
    Apply only to relevant platforms (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Lionel Landwerlin 0cd93c59ef intel/compiler: add primitive rate output support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Lionel Landwerlin cebf284ac1 intel/compiler: add a new pass to lower shading rate into HW format
Rework:
 * Jason: Modernize brw_nir_lower_shading_rate_output:
   1. Use nir_shader_instructions_pass()
   2. Use *_imm builder helpers.
   3. Use nir_intrinsic_base() instead of ->const_index[0]

v2: Also lower loads (Caio)

v3: Update stage check to trigger lowering (Caio)

v4: Assert on != MESH (Caio)

v5: Fixup instruction insertion (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Lionel Landwerlin 3ab7f4471c isl: disable CPB surface compression
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Lionel Landwerlin dff08cbf8e isl: add support for coarse pixel control surfaces
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.

v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)

v3: Drop unused macro (Nanley)
    s/isl_to_gen/isl_encode/ (Nanley)
    Remove pitch alignment 128B constraint already covered by tiling (Nanley)
    Move some asserts together (Nanley)

v4: Disable miptail for now (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Lionel Landwerlin 8d90fe587f intel/dev: details CPS feature support
DG2 introduces per primitive coarse pixel settings (in stages
preceding the PS shader) and also a control surface specifying the
rate at through the resulting surface.

v2: update comment (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Lionel Landwerlin 8bdbc93a9d genxml: add new 3DSTATE_PS_EXTRA bit
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Lionel Landwerlin ea71fb0b4b genxml: gen12.5 changes for CPS
v2: Make genxml look more like BSpec (Caio)
    Fixup X_Focal/Y_Focal entries (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
2022-02-02 17:09:46 +00:00
Nanley Chery f724f95542 intel/isl: Add more PRM text for HiZ/STC requirement
Add text describing why HierarchicalDepthBufferEnable must be set along
with SeparateStencilBufferEnable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
2022-02-02 16:25:10 +00:00
Nanley Chery bc9ce9705c intel/isl: Fix depth buffer TiledSurface programming
The assert for the TiledSurface field caught a programming error, but
with a segfault instead of the usual route of assert-failing. We only
set this field when we have a depth surface, but we also need to set it
when one isn't provided. Fix this issue and drop the assert.

Fixes: b77d694223 ("intel/isl: Allow HiZ with Tile4/64 surfaces")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5950
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
2022-02-02 16:25:10 +00:00
Nanley Chery 146213d0ee intel/isl: Simplify Z-buffer tiling config during emit
For SNB and prior, assert that the surface is Y-tiled and use constants
when configuring the tiling parameters. This makes a follow-on commit
clearer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
2022-02-02 16:25:10 +00:00
Iván Briano 965d58b058 anv: Report the right conformance version
Fixes: df8ac77af8 ("anv: Advertise Vulkan 1.3")

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14827>
2022-02-01 14:36:18 -08:00
Iván Briano ea0fa5c6bc anv: Handle resolveImageLayout on dynamic rendering
Fixes: 5d9e8bc9be ("anv: implement the meat of VK_KHR_dynamic_rendering")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5942

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14812>
2022-02-01 19:51:23 +00:00
Caio Oliveira 8bab8f6422 compiler, intel: Add gl_shader_stage_is_mesh()
And replace the previous Intel-specific function.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14823>
2022-02-01 17:41:25 +00:00
Connor Abbott 913bec10c4 nir/lower_subgroups: Rename lower_shuffle to lower_relative_shuffle
This option only applies to relative shuffles (up/down/xor), and in a
moment we're going to add an option to lower normal shuffles, so rename
it.

While we're here, rename lower_shuffle() to lower_to_shuffle() for
similar reasons.

Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14412>
2022-02-01 16:27:45 +00:00
Lionel Landwerlin 928156bc9d intel/tracepoint: simplify tracepoint descriptions
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14818>
2022-02-01 09:28:30 +00:00
Jason Ekstrand d85a9d658f anv/image: Call into WSI to create swapchain images
This guarantees that we get an image that's created with exactly the
swapchain image creation parameters instead of trying to emulate it
inside the driver.  Ideally, we'd use the fancy new bind helper too but
our magic ANV_IMAGE_MEMORY_BINDING_PRIVATE gets in the way and we really
do want to re-bind ourself.

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12031>
2022-01-31 19:46:55 +00:00
Jason Ekstrand a2e986b6d9 anv/image: Add some asserts when binding swapchain images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12031>
2022-01-31 19:46:55 +00:00
Jason Ekstrand ca791f5c5d wsi/common: Set VK_IMAGE_CREATE_ALIAS_BIT
With Vulkan 1.1, we have a VkImageSwapchainCreateInfoKHR struct which
lets you create a new VkImage which aliases a swapchain image.  However,
there is no corresponding swapchain create flag so we have to set
VK_IMAGE_CREATE_ALIAS_BIT all the time.

We need to do a bit of work in ANV to prevent it from asserting the
moment it sees one of these.  Fortunately, they're already safe because
WSI images go through a different bind path for
VkBindImageMemorySwapchainInfoKHR.

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12031>
2022-01-31 19:46:55 +00:00
Thomas H.P. Andersen ac59a266cc anv: drop a set but unused variable
Fixes a warning with clang

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14790>
2022-01-31 16:10:31 +00:00
Thomas H.P. Andersen bdfb1885b8 anv: drop a set but unused variable
Fixes a warning with clang

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14790>
2022-01-31 16:10:31 +00:00
Thomas H.P. Andersen 8e4b3cf832 anv: avoid warning about unused function
This function is only used if GFX_VER == 7

Fixes a clang warning about unused static inlined functions.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14790>
2022-01-31 16:10:31 +00:00
Lionel Landwerlin d6e457c0a4 anv: tidy long lines in descriptor code
No functional change.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14799>
2022-01-31 14:55:48 +00:00
Marcin Ślusarz 24fef8f33d intel/compiler: Use Task/Mesh InlineData for the first few push constants
Replace load_mesh_global_arg_addr_intel with a more general intrinsic
load_mesh_inline_data_intel, since inline data now hold both
a pointer descriptor information and the first few push constants.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14788>
2022-01-29 06:32:19 +00:00
Marcin Ślusarz 1d9f47325b intel/compiler: handle gl_[Clip|Cull]Distance from mesh in fragment shaders
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14788>
2022-01-29 06:32:19 +00:00
Marcin Ślusarz baa17865de intel/compiler: handle gl_[Clip|Cull]Distance in mesh shaders
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14788>
2022-01-29 06:32:19 +00:00
Caio Oliveira 856a0cacb1 intel/compiler: Merge Per-Primitive attribute handling in Mesh case
Just a refactor, no behavior change.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14788>
2022-01-29 06:32:19 +00:00
Caio Oliveira 2b8b884bcd intel/compiler: Have specific mesh handling in calculate_urb_setup()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14788>
2022-01-29 06:32:19 +00:00
Caio Oliveira 8599ded193 intel: Only reserve space for Compute Engine out of URB in Gfx12LP
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14756>
2022-01-28 14:52:17 -08:00
Caio Oliveira d6c31f05a2 anv: Fix subgroupSupportedStages physical property
Use the proper Vulkan values that can be combined into a bitmask.

Fixes: f40a08d25c ("anv: Don't advertise unsupported shader stages")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14761>
2022-01-28 01:13:07 -08:00
Nanley Chery 7f46e569e5 intel/isl: Support the XeHP media compression format
The format on this platform is slightly different from the one used on
TGL. Also it's part of the surface state instead of an aux-map.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
2022-01-28 00:30:55 +00:00
Nanley Chery fde43bb194 intel: Rename a RenderCompressionFormat field
The name of the bit field is CompressionFormat. The format subsections
of the field specify the alternate names of RenderCompressionFormat or
MediaCompressionFormat depending on the compression type.

We're going to start programming this field for media compression, so
we'd like to use either the bit field name or a new
MediaCompressionFormat field. Either option seems fine, so we go with
the first.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
2022-01-28 00:30:55 +00:00
Nanley Chery cc973de5f6 intel/isl: Support YUV pipe-to-isl format mapping
This will help to configure surfaces for media compression.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
2022-01-28 00:30:55 +00:00
Nanley Chery 749b82238b isl: Enable compression with multisampled Tile64
We haven't tested the single-sampled case, so this doesn't enable any
more uses of standalone CCS. This does however, allow multisampled
surfaces with MCS or HIZ to get upgraded to MCS_CCS and HIZ_CCS,
respectively.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
2022-01-27 22:38:01 +00:00
Jordan Justen 792e294572 isl: Enable compression with Tile4
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
2022-01-27 22:38:01 +00:00
Nanley Chery 793338266c anv: Don't allocate VMA for CCS on XeHP
On XeHP, CCS doesn't require VMA on XeHP. The HW provides anything
allocated in LMEM a mapping to a CCS memory range for free. So, we:

1) use the implicit CCS framework to avoid adding an image memory
   binding for the CCS surface.
2) leave each BO sized as-is instead of adding on space for the CCS.
   Thankfully the framework only adds on space if an aux-map is present.
   XeHP has no aux-map, so this patch doesn't explicitly do anything for
   this.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
2022-01-27 22:38:01 +00:00
Nanley Chery 382f6ccda8 anv: Require the local heap for CCS on XeHP
This platform doesn't support CCS in system memory.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
2022-01-27 22:38:01 +00:00
Nanley Chery 93f8d88fa3 anv: Disable the SMEM fallback for local memory
The fallback is incompatible with allocations that use CCS on XeHP. On
that platform, compression can't be used in SMEM.

Apps should be okay with this change. They're able to manage local and
system memory heaps directly (see VK_EXT_memory_budget).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
2022-01-27 22:38:01 +00:00
Nanley Chery 63096b886f anv: Drop redundant disabling of non-renderable CCS
ISL reports no CCS support for these formats, except for
R10G10B10A2_UNORM_SRGB. Anv doesn't support that format at all however.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14431>
2022-01-27 22:38:01 +00:00
Lionel Landwerlin 583e4549fe intel/ci: expected failure for 1.3 with older CTS
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14706>
2022-01-27 16:42:01 +00:00
Jason Ekstrand df8ac77af8 anv: Advertise Vulkan 1.3
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14706>
2022-01-27 16:42:01 +00:00
Lionel Landwerlin 7d9cd208d5 anv: switch a bunch of struct/enum to 1.3 versions
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14706>
2022-01-27 16:42:01 +00:00
Jason Ekstrand 2e730167a4 anv: Implement 1.3 features/properties
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14706>
2022-01-27 16:42:01 +00:00
Caio Marcelo de Oliveira Filho 372faa4a23 anv: SPIR-V 1.6 shaders imply ALLOW_VARYING_SUBGROUP_SIZE
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14706>
2022-01-27 16:42:01 +00:00
Mike Blumenkrantz fe3984b8cd anv: silence wsi debug logging
this is triggered by mesa's own wsi handling, so stop printing nonsense

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14743>
2022-01-27 13:10:27 +00:00
Nanley Chery 57445adc89 anv: Re-enable CCS_E on TGL+
Commit e614789588 ("anv: Also disallow CCS_E for multi-LOD images")
accidentally disabled CCS_E on TGL+ because it checked for
image->vk.mip_levels > 0 instead of image->vk.mip_levels > 1.

Instead of reverting it, we remove the code which disables CCS_E for
mipmapped or arrayed images now that we've sufficiently handled the
clear color issue in other ways.

Fixes: e614789588 ("anv: Also disallow CCS_E for multi-LOD images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14723>
2022-01-26 23:34:33 +00:00
Nanley Chery c48401404c anv: Use ANV_FAST_CLEAR_DEFAULT_VALUE for CCS on TGL+
On TGL, if a block of fragment shader outputs match the surface's clear
color, the HW may convert them to fast-clears (see HSD 14010672564).
This can lead to rendering corruptions if not handled properly. We
restrict the clear color to zero to avoid issues that can occur with:

   - Texture view rendering (including blorp_copy calls)
   - Images with multiple levels or array layers

Fixes: e614789588 ("anv: Also disallow CCS_E for multi-LOD images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14723>
2022-01-26 23:34:33 +00:00
Nanley Chery d68b2db89c anv: Disable CCS_E for some 8/16bpp copies on TGL+
CCS_E is currently disabled on TGL+, but we'll enable it soon. We choose
to explicitly disable it for certain copy operations to avoid CTS
failures in the following groups:

- dEQP-VK.drm_format_modifiers.export_import.*
- dEQP-VK.synchronization*

Fixes: e614789588 ("anv: Also disallow CCS_E for multi-LOD images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14723>
2022-01-26 23:34:33 +00:00
Nanley Chery 09ca089144 anv: Drop assert against modifier with aux on gfx12
Commit b664349973 ("anv: Enable implicit CCS for external images")
introduced support for implicit CCS with I915_FORMAT_MOD_Y_TILED.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14723>
2022-01-26 23:34:33 +00:00
Iván Briano 61ece8f6a4 anv: Enable VK_KHR_dynamic_rendering
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
2022-01-25 18:13:51 -08:00