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Author SHA1 Message Date
Jason Ekstrand 73b3efcd59 anv: Handle the null FS optimization after compiling shaders 
Actually compile and cache the no-op fragment shader but remove it from
the pipeline if we determine it's a no-op.  This way we always have it
even if it's not strictly needed.

Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
 2022-05-27 14:33:53 +00:00
Jason Ekstrand 9fe6caf4e7 anv: Drop alpha_to_coverage from the NULL FS optimization 
Starting with Ivy Bridge, we implement alpha-to-coverage by writting
gl_SampleMask with a pattern based on alpha.  This will show up in
wm_prog_data::uses_omask so we don't need to look at the key.

Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
 2022-05-27 14:33:53 +00:00
Jason Ekstrand 1b9248e761 intel/fs: Copy color_outputs_valid into wm_prog_data 
Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
 2022-05-27 14:33:53 +00:00
Jason Ekstrand 8379993223 intel/fs: Drop fs_visitor::emit_alpha_to_coverage_workaround() 
It no longer exists.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16506>
 2022-05-27 14:33:53 +00:00
David Heidelberg b19c858f3d ci/intel: add RoR and Nheko traces and reenable most of Valve traces 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16633>
 2022-05-27 06:51:38 +00:00
Lionel Landwerlin e666089082 intel/disasm: add missing handling of <1;1,0> 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7cd9adeb41 ("intel/compiler: In XeHP prefer <1;1,0> regions before compacting")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16704>
 2022-05-26 06:42:16 +00:00
Kenneth Graunke 9886615958 intel/compiler: Move spill/fill tracking to the register allocator 
Originally, we had virtual opcodes for scratch access, and let the
generator count spills/fills separately from other sends.  Later, we
started using the generic SHADER_OPCODE_SEND for spills/fills on some
generations of hardware, and simply detected stateless messages there.

But then we started using stateless messages for other things:
- anv uses stateless messages for the buffer device address feature.
- nir_opt_large_constants generates stateless messages.
- XeHP curbe setup can generate stateless messages.

So counting stateless messages is not accurate.  Instead, we move the
spill/fill accounting to the register allocator, as it generates such
things, as well as the load/store_scratch intrinsic handling, as those
are basically spill/fills, just at a higher level.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16691>
 2022-05-25 06:56:01 +00:00
Michael Skorokhodov 10b6d9230c anv: Update line range 
This commit increases the maximum line width to 8.0 for SLK+
and to 7.9921875 for BDW and earlier.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6234
Fixes: fce0027d ("anv: Unbreak wide lines on HSW/BDW")
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15879>
 2022-05-24 23:09:26 +00:00
Kenneth Graunke 59bfc9c6cb intel: Fix analysis invalidation in eliminate_find_live_channel 
If we saw a HALT instruction, we would forget to invalidate our analysis
pass information before returning progress.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16677>
 2022-05-24 22:36:39 +00:00
Marcin Ślusarz 21d3630cbc intel/tools: fix 32-bit build 
Fixes: 0aac3b1009 ("intel/tools/aubinator: add support for 2 "new" subopcodes")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6553
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16695>
 2022-05-24 18:27:32 +00:00
Viktoriia Palianytsia e39a5f2b9f anv: Add workaround for sample mask with multisampling 
The game Batman: Arkham Knight expects OpenGL behavior
with sample mask and multisampling which is different
from the Vulkan one.
This workaround fix changes key->ignore_sample_mask_out
value that is used for
prog_data->uses_omask definition in brv_fs.cpp(9740)
In that way prog_data->uses_omask also changes it value
and the cloak stops flickering.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6078

Signed-off-by: Viktoriia Palianytsia <v.palianytsia@globallogic.com>

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16551>
 2022-05-24 14:43:57 +00:00
Marcin Ślusarz 8187716b55 intel/tools: add macros for gfx12+ variant of VCSUNIT0 
Not used for now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16664>
 2022-05-24 08:03:45 +00:00
Marcin Ślusarz ba80c36708 intel/tools/aubinator: list all platforms in help message 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16664>
 2022-05-24 08:03:45 +00:00
Marcin Ślusarz 0aac3b1009 intel/tools/aubinator: add support for 2 "new" subopcodes 
... and add macros for subopcodes we haven't seen yet

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16664>
 2022-05-24 08:03:44 +00:00
Marcin Ślusarz 43ad5fd9b7 intel/tools: drop wrappers around mmio regs macros 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16664>
 2022-05-24 08:03:44 +00:00
Marcin Ślusarz b916b30f58 intel/tools: clean up mmio regs definitions 
Each unit has the same regs at the same offsets.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16664>
 2022-05-24 08:03:44 +00:00
Marcin Ślusarz 3910736f29 intel/tools: add support for GEM_CREATE_EXT in intel_dump_gpu 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16664>
 2022-05-24 08:03:44 +00:00
Jason Ekstrand c24aa449d0 vulkan,anv,turnip: Add a common CmdBindVertexBuffers wrapper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611>
 2022-05-20 02:12:37 +00:00
Kenneth Graunke 27314718a3 intel: Drop Wa_1409226450 (stall before instruction cache invalidation) 
Production Tigerlake and DG1 hardware shouldn't need this workaround.
It was only needed on the very first steppings which never went public.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16575>
 2022-05-19 21:31:45 +00:00
Lionel Landwerlin 1c077ca9c0 u_trace/anv/iris: drop cs argument for recording traces 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16605>
 2022-05-19 19:04:28 +00:00
Lionel Landwerlin 5398c9183e intel/ds: fix compilation 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6518
Fixes: efc2782f97 ("intel/perf: store a copy of devinfo")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16601>
 2022-05-19 16:42:41 +00:00
Lionel Landwerlin 9d0db8d4c4 intel/perf: deal with OA reports timestamp values on DG2 
OA reports on XeHP have their timestamp shifted to the left by 1. To
get that back in the same time domain as the REG_READ you need to
shift it back to the right and you're loosing the top bit.

v2: use ull for 64bit constant (Ian)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin 773f41e3e4 intel/perf: disable sseu setting on Gfx12.5+ 
This is rejected by i915.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin d2834dd626 intel/perf: add new layout for Gfx12.5 products 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin 66045acdf9 intel/perf: add max vfuncs 
New counters will use those from inside their read function to
generate percentage numbers.

v2: Forgot to update Iris (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin c740ca6000 intel/perf: add support new variable counting the number of EUs in slice0-3 
v2: MIN2(4, max_slices) (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin 6f63bc38e7 intel/perf: add OA A counter type 
On Gfx12.5 products, we'll need to capture a couple of A counters that
are not captured in MI_RPC reports. Those are actually global,
previously all A counters were per context.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin 376e420abb intel/perf: stop overriding oa_format 
This already set in the intel_perf_setup.h file at metric set
creation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin aa04b47c6e intel/perf: add support for GtSlice/GtSliceXDualsubsliceY variables 
For those, we'll fish the information out of the devinfo.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin d134a62345 intel/perf: add support for dualsubslice count variable 
This is the same as the subslice count.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin efc2782f97 intel/perf: store a copy of devinfo 
In the future we'll pull more information off devinfo.

v2: Constify pointers (Ian)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Lionel Landwerlin 0df4b96062 intel/perf: add support for new opcodes in code generation 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16144>
 2022-05-17 19:55:10 +00:00
Jason Ekstrand fc8d2543fc vulkan,v3dv: Add a driver_internal flag to vk_image_view_init/create 
We already had a little workaround for v3dv where, for some if its meta
ops, it had to bind a depth/stenicil image as color.  Instead of
special-casing binding depth/stencil as color, let's flip on the
drier_internal flag and get rid of most of the checks in that case.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
 2022-05-17 18:14:55 +00:00
Kenneth Graunke b637f6c3db intel/decoder: Fix binding table pointer decoding with large offsets 
XeHP supports a 20:5 pointer format, so the offset can legitimately
be more than UINT16_MAX.  Likewise, with 256B binding table mode on
Icelake/Tigerlake, we might have 18:8 pointers that exceed UINT16_MAX.

Thanks to Felix DeGrood for catching this!

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16538>
 2022-05-17 08:52:00 +00:00
David Heidelberg d22eeb5ae0 ci/iris: skqp: remove flaking atlastext for TGL 
Example:
 - https://gitlab.freedesktop.org/mesa/mesa/-/jobs/22380389#L4349
 - https://mesa.pages.freedesktop.org/-/mesa/-/jobs/22380389/artifacts///results/gles/report.html

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6460
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
 2022-05-17 06:57:19 +00:00
David Heidelberg 317496ba8a ci/iris: skqp: add default GLES rendertests for TGL 
Import the intact whole rendertest file from skqp (branch
android-cts-12.1_r1) to be able remove the offending test line in the
following commit.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16407>
 2022-05-17 06:57:19 +00:00
Timothy Arceri d7a071a28f gallium/drivers: set force_indirect_unrolling_sampler for all required drivers 
This is set to true for all drivers that have a GLSL level
of support lower than 4.00. This matches the rule for setting the
GLSL IR option EmitNoIndirectSampler.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Lionel Landwerlin 17fc7b20b1 anv: fix primitives generated queries values 
Numbers in some situations are incorrect because we don't stall
properly before capturing the register value.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6412
Fixes: a468f26ca5 ("anv: implement VK_EXT_primitives_generated_query")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16505>
 2022-05-14 10:47:29 +00:00
Marcin Ślusarz 1542ab70eb anv: handle primitive shading rate for mesh 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16030>
 2022-05-13 13:05:51 +00:00
Marcin Ślusarz 9acb30c8c4 intel/compiler: implement primitive shading rate for mesh 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16030>
 2022-05-13 13:05:51 +00:00
Marcin Ślusarz aa1c128b54 anv: disable streamout before emitting mesh shading state 
Fixes tests which use secondary command buffers.

Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
 2022-05-13 09:43:02 +00:00
Marcin Ślusarz 29a778fa6b intel/compiler: print name of the unhandled intrinsic 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
 2022-05-13 09:43:02 +00:00
Marcin Ślusarz f083df8710 anv: update task/mesh distribution with the recommended values 
Fixes: ef04caea9b ("anv: Implement Mesh Shading pipeline")

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
 2022-05-13 09:43:02 +00:00
Marcin Ślusarz 65ff6932dc intel/compiler: handle gl_Viewport and gl_Layer in FS URB setup 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
 2022-05-13 09:43:02 +00:00
Marcin Ślusarz 040062df41 intel/compiler: handle VARYING_SLOT_CULL_PRIMITIVE in mesh 
It's needed for gl_MeshPerPrimitiveNV[].gl_ViewportMask

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16493>
 2022-05-13 09:43:02 +00:00
Vadym Shovkoplias 55c71217ec driconf: Add a limit_trig_input_range option 
With this option enabled range of input values for fsin and fcos is
limited to [-2*pi : 2*pi] by calculating the reminder after 2*pi modulo
division. This helps to improve calculation precision for large input
arguments on Intel.

-v2: Add limit_trig_input_range option to prog_key to update shader
     cache (Lionel)

Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16388>
 2022-05-13 06:47:53 +00:00
Kenneth Graunke ad537edc7c anv: Fix INTEL_DEBUG=bat on XeHP 
We no longer emit STATE_BASE_ADDRESS in every batch on XeHP, so the
decoder might not know what the various base addresses are if it's only
looking at a single batch.  Fortunately, they also never change, so we
can just emit them once here.

On earlier platforms, initializing them here should be harmless.  We'll
emit STATE_BASE_ADDRESS if we change them, which will update these.

Thanks to Iván Briano for catching this.

Fixes: 8831cb38aa ("anv: Stop updating STATE_BASE_ADDRESS on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16287>
 2022-05-12 11:10:25 -07:00
Jordan Justen ad565f6b70 intel/dev: Enable first set of DG2 PCI IDs 
Mostly Matt Roper's kernel patch commit message:

The IDs added here are the subset reserved for 'motherboard down'
designs of DG2. We have all the necessary support upstream to enable
these now.

The remaining DG2 IDs for add-in cards will be enabled in a future
patch once some additional required functionality has fully landed.

Ref: https://patchwork.freedesktop.org/patch/msgid/20220425211251.77154-3-matthew.d.roper@intel.com
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
 2022-05-12 03:03:57 -07:00
Jordan Justen 4456209ce5 intel/dev: Add INTEL_PLATFORM_DG2_G12 
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>
 2022-05-12 03:03:57 -07:00
Jason Ekstrand 352e32e5ba nir/builder: Add a nir_trim_vector helper 
This pattern pops up a bunch and the semantics of nir_channels() aren't
very convenient much of the time.  Let's add a nir_trim_vector() which
matches nir_pad_vector().

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>
 2022-05-11 14:47:33 +00:00