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Author SHA1 Message Date
Mark Janes 3c9a8f7a6d intel/dev: generate helpers to identify platform workarounds 
Workarounds for defects in Intel silicon have been manually
implemented:

 - consult defect database for the current platform

 - add workaround code behind platform ifdef or devinfo->ver checks

Some bugs have occurred due to the manual process.  Typical failure
modes:

 - defect database is updated after a platform is enabled

 - version checks are overly broad (eg gfx11+) for defects that were
   fixed (eg in gfx12)

 - version checks are too narrow for defects that were extended to
   subsequent platforms.

 - missed workarounds

This commit automates workaround handling:

 - Internal automation queries the defect database to collate and
   summarize defect documentation in json.

 - mesa_defs.json describes all public defects and impacted platforms.
   Defects which are extended to subsequent platforms are listed under
   the original defect.

 - gen_wa_helpers.py generates workaround helpers to be called
   in place of version checks:

   - NEEDS_WORKAROUND_{ID} provides a compile time check suitable for
     use in genX routines.

   - intel_device_info_needs_wa() provides a more precise runtime
     check, differentiating platforms within a generation and
     platform steppings.

Internal automation will generate new mesa_defs.json as needed.
Workarounds enabled with these helpers will apply correctly based on
updated information in Intel's defect database.

Reviewed-by: Dylan Baker <dylan@pnwbakers>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Dylan Baker a0fa31bcdd intel/dev: create a helper dependency for libintel_dev 
This ensures that users of libintel_dev.a won't be compiled until
include files are generated, and that they are recompiled when the
header changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20825>
 2023-03-02 00:01:27 +00:00
Iván Briano 4887b88d22 anv: use the parameter passed to the macro 
The two points calling this macro pass dyn->rs.provoking_vertex to it,
which is why it works, but it's cleaner to use the parameter instead.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21613>
 2023-03-01 19:07:41 +00:00
Dylan Baker a8691f916b intel/mi: use 64bit constant for bitshift 
Coverity complains that we could end up rolling over on a 32bit
platform, which isn't really true because of the assertion, but there's
also no harm in ensuring that we have exactly the same behavior for both
32 bit and 64 bit platforms.

CID: 1515989
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21572>
 2023-03-01 18:42:25 +00:00
Timothy Arceri d75a36a9ee glsl: remove do_copy_propagation_elements() optimisation pass 
Since 13b859de do_copy_propagation_elements() has a flaw where
the time it takes to complete grows exponentially slowers as the number
of nested loops increases. It can also hurt rather than help verses
just letting NIR optimise the code. So if the NIR linker is enabled we
let it handle it instead.

shader-db results Iris (BDW):

total instructions in shared programs: 11177181 -> 11199739 (0.20%)
instructions in affected programs: 119424 -> 141982 (18.89%)
helped: 109
HURT: 65
total cycles in shared programs: 368946819 -> 372277173 (0.90%)
cycles in affected programs: 116539428 -> 119869782 (2.86%)

total spills in shared programs: 3983 -> 8785 (120.56%)
spills in affected programs: 2072 -> 6874 (231.76%)
helped: 0
HURT: 6

total fills in shared programs: 2016 -> 6068 (200.99%)
fills in affected programs: 230 -> 4282 (1761.74%)
helped: 0
HURT: 6

LOST:   85
GAINED: 77

freedreno results:

total instructions in shared programs: 11011122 -> 11011620 (<.01%)
instructions in affected programs: 939829 -> 940327 (0.05%)
total full in shared programs: 762725 -> 762674 (<.01%)
full in affected programs: 1096 -> 1045 (-4.65%)
total constlen in shared programs: 1772092 -> 1771596 (-0.03%)
constlen in affected programs: 2780 -> 2284 (-17.84%)
total stp in shared programs: 4040 -> 4058 (0.45%)
stp in affected programs: 3656 -> 3674 (0.49%)
total ldp in shared programs: 2160 -> 2178 (0.83%)
ldp in affected programs: 1748 -> 1766 (1.03%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/13.shader_test CL: 1231 -> 1234 (0.24%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/13.shader_test CL: 1231 -> 1234 (0.24%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/15.shader_test CL: 453 -> 456 (0.66%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/15.shader_test CL: 453 -> 456 (0.66%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_high_off/17.shader_test CL: 144 -> 147 (2.08%)
stp HURT:   shaders/robclark-shaders/gfxbench5/gl_5_normal_off/17.shader_test CL: 144 -> 147 (2.08%)

however, those stp counts are misleading -- gfxbench gl-5-normal actually
gets its scratch (ldp/stp) stored as 16 bits instead of 32 thanks to
better NIR copy prop, and the result is 2.64398% +/- 0.0991923% perf
improvement!

i915 results:

total instructions in shared programs: 510528 -> 510489 (<.01%)
instructions in affected programs: 3303 -> 3264 (-1.18%)
total tex_indirect in shared programs: 16708 -> 16717 (0.05%)
tex_indirect in affected programs: 134 -> 143 (6.72%)
total temps in shared programs: 30181 -> 30169 (-0.04%)
temps in affected programs: 1268 -> 1256 (-0.95%)
LOST:   0
GAINED: 1

i915 highlights:
instructions HURT:   shaders/closed/steam/legend-of-grimrock/47.shader_test FS: 141 -> 144 (2.13%)
instructions HURT:   shaders/closed/steam/steamworld-dig/22.shader_test FS: 84 -> 108 (28.57%)
temps HURT:   shaders/closed/steam/left-4-dead-2/medium/3682.shader_test FS: 7 -> 13 (85.71%)

r300 results:

total instructions in shared programs: 1340439 -> 1340845 (0.03%)
instructions in affected programs: 32354 -> 32760 (1.25%)
total temps in shared programs: 179394 -> 179329 (-0.04%)
temps in affected programs: 1505 -> 1440 (-4.32%)
total consts in shared programs: 1177742 -> 1177885 (0.01%)
consts in affected programs: 1107 -> 1250 (12.92%)
total lits in shared programs: 24992 -> 25019 (0.11%)
lits in affected programs: 138 -> 165 (19.57%)
instructions HURT:   shaders/closed/steam/legend-of-grimrock/26.shader_test FS: 47 -> 52 (10.64%)
instructions HURT:   shaders/closed/steam/sanctum-2/6072.shader_test FS: 43 -> 48 (11.63%)
instructions HURT:   shaders/closed/steam/champions-of-regnum/2378.shader_test VS: 35 -> 40 (14.29%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13288>
 2023-03-01 16:09:25 +00:00
Lionel Landwerlin 42e8a2c1d6 genxml: fix border color offset field on Gfx12+ 
I wonder if the docs are correct for Gfx11 because this is the
generation that gave us the Bindless Sampler Heap of 4Gb. So it would
make sense that the border colors can also be placed anywhere in that
4Gb heap.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21600>
 2023-03-01 08:45:11 +00:00
Lionel Landwerlin 58b687d77b genxml: Fix STATE_BASE_ADDRESS::BindlessSurfaceStateSize field size 
BSpec 44507

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21600>
 2023-03-01 08:45:11 +00:00
Dave Airlie 1f0fdcb619 anv: always pick graphics queue to execute prime blits on. 
This will change when we get transfer queues but this should avoid
video queues being picked by accident.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21204>
 2023-03-01 03:37:36 +00:00
Lionel Landwerlin 672b2f9ad1 anv: remove more Gfx7 code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21599>
 2023-02-28 23:49:27 +00:00
Lionel Landwerlin 3cd72a2840 anv: fixup Wa_16011107343 for Gfx12 only 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 75968398f3 ("anv: emit 3DSTATE_HS for each primitive on gfx12")
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21605>
 2023-02-28 23:03:21 +00:00
Marcin Ślusarz e74a3284f5 anv: halve the push constants space in mesh pipelines 
It's only used by fragment shaders, so halving it matches the size
used in the most optimal primitive pipeline (VS + FS).

This change frees some URB space for mesh and task shaders and as
a result improves vk_meshlet_cadscene performance by up to 2%,
depending on the model.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21559>
 2023-02-28 20:18:01 +00:00
David Heidelberg baea3b328b intel/vulkan: add missing dependency on generated headers 
Adding correct dependencies prevents occasional build flakes with parallel builds.

```
FAILED: src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o
ccache cc -Isrc/intel/vulkan/libanv_common.a.p -Isrc/intel/vulkan -I../src/intel/vulkan -Iinclude -I../include -Isrc -I../src -Isrc/mapi -I../src/mapi -Isrc/mesa -I../src/mesa -I../src/gallium/include -Isrc/intel -I../src/intel -Isrc/compiler -I../src/compiler -Isrc/compiler/nir -I../src/compiler/nir -Isrc/vulkan/util -I../src/vulkan/util -Isrc/vulkan/runtime -I../src/vulkan/runtime -Isrc/vulkan/wsi -I../src/vulkan/wsi -Isrc/intel/genxml -Isrc/intel/vulkan/shaders -Isrc/intel/ds -I/usr/local/include -I/usr/local/include/libdrm -fvisibility=hidden -fdiagnostics-color=always -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -std=c11 -O2 -g -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS '-DPACKAGE_VERSION="23.1.0-devel"' '-DPACKAGE_BUGREPORT="https://gitlab.freedesktop.org/mesa/mesa/-/issues"' -DHAVE_OPENGL=1 -DHAVE_OPENGL_ES_1=1 -DHAVE_OPENGL_ES_2=1 -DHAVE_SWRAST -DHAVE_VIRGL -DHAVE_RADEONSI -DHAVE_ZINK -DHAVE_CROCUS -DHAVE_IRIS -DHAVE_I915 -DVIDEO_CODEC_VC1DEC=1 -DVIDEO_CODEC_H264DEC=1 -DVIDEO_CODEC_H264ENC=1 -DVIDEO_CODEC_H265DEC=1 -DVIDEO_CODEC_H265ENC=1 -DHAVE_X11_PLATFORM -DHAVE_SURFACELESS_PLATFORM -DHAVE_DRM_PLATFORM -DHAVE_XCB_PLATFORM -DHAVE_ST_VDPAU -DENABLE_ST_OMX_BELLAGIO=0 -DENABLE_ST_OMX_TIZONIA=0 -DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING -DGLX_USE_DRM -DALLOW_KCMP -DENABLE_SHADER_CACHE -DHAVE___BUILTIN_BSWAP32 -DHAVE___BUILTIN_BSWAP64 -DHAVE___BUILTIN_CLZ -DHAVE___BUILTIN_CLZLL -DHAVE___BUILTIN_CTZ -DHAVE___BUILTIN_EXPECT -DHAVE___BUILTIN_FFS -DHAVE___BUILTIN_FFSLL -DHAVE___BUILTIN_POPCOUNT -DHAVE___BUILTIN_POPCOUNTLL -DHAVE___BUILTIN_UNREACHABLE -DHAVE___BUILTIN_TYPES_COMPATIBLE_P -DHAVE_FUNC_ATTRIBUTE_CONST -DHAVE_FUNC_ATTRIBUTE_FLATTEN -DHAVE_FUNC_ATTRIBUTE_MALLOC -DHAVE_FUNC_ATTRIBUTE_PURE -DHAVE_FUNC_ATTRIBUTE_UNUSED -DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT -DHAVE_FUNC_ATTRIBUTE_WEAK -DHAVE_FUNC_ATTRIBUTE_FORMAT -DHAVE_FUNC_ATTRIBUTE_PACKED -DHAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL -DHAVE_FUNC_ATTRIBUTE_ALIAS -DHAVE_FUNC_ATTRIBUTE_NORETURN -DHAVE_FUNC_ATTRIBUTE_VISIBILITY -DHAVE_UINT128 -DHAVE_REALLOCARRAY -D_GNU_SOURCE -DUSE_SSE41 -DUSE_GCC_ATOMIC_BUILTINS -DUSE_X86_64_ASM -DMAJOR_IN_SYSMACROS -DHAS_SCHED_H -DHAS_SCHED_GETAFFINITY -DHAVE_LINUX_FUTEX_H -DHAVE_ENDIAN_H -DHAVE_DLFCN_H -DHAVE_SYS_SHM_H -DHAVE_CET_H -DHAVE_SYS_INOTIFY_H -DHAVE_STRTOF -DHAVE_MKOSTEMP -DHAVE_TIMESPEC_GET -DHAVE_MEMFD_CREATE -DHAVE_RANDOM_R -DHAVE_FLOCK -DHAVE_STRTOK_R -DHAVE_GETRANDOM -DHAVE_GNU_QSORT_R -DHAVE_STRUCT_TIMESPEC -DHAVE_PROGRAM_INVOCATION_NAME -DHAVE_ISSIGNALING -DHAVE_POSIX_MEMALIGN -DHAVE_DIRENT_D_TYPE -DHAVE_STRTOD_L -DHAVE_DLADDR -DHAVE_DL_ITERATE_PHDR -DSUPPORT_INTEL_INTEGRATED_GPUS -DHAVE_ZLIB -DHAVE_COMPRESSION -DHAVE_PTHREAD -DHAVE_PTHREAD_SETAFFINITY -DHAVE_LIBDRM -DLLVM_AVAILABLE '-DMESA_LLVM_VERSION_STRING="13.0.1"' -DLLVM_IS_SHARED=1 -DDRAW_LLVM_AVAILABLE -DUSE_LIBELF -DMESA_EXECMEM -DHAVE_LIBUNWIND -DHAVE_OPENMP -DHAVE_DRI -DHAVE_DRI2 -DHAVE_DRI3 -DHAVE_DRI3_MODIFIERS -DHAVE_DRISW_KMS -DHAVE_PERFETTO -mtls-dialect=gnu2 -Werror=implicit-function-declaration -Werror=missing-prototypes -Werror=return-type -Werror=empty-body -Werror=incompatible-pointer-types -Werror=int-conversion -Wimplicit-fallthrough -Wmisleading-indentation -Wno-missing-field-initializers -Wno-format-truncation -Wno-nonnull-compare -fno-math-errno -fno-trapping-math -fno-common -Wno-unused-function -Werror=format -Wformat-security -ffunction-sections -fdata-sections -fPIC -DVK_USE_PLATFORM_XCB_KHR -DVK_USE_PLATFORM_XLIB_KHR -DVK_USE_PLATFORM_DISPLAY_KHR -DVK_USE_PLATFORM_XLIB_XRANDR_EXT -Wno-override-init -DANV_SUPPORT_RT=0 -MD -MQ src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o -MF src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o.d -o src/intel/vulkan/libanv_common.a.p/anv_generated_indirect_draws.c.o -c ../src/intel/vulkan/anv_generated_indirect_draws.c
../src/intel/vulkan/anv_generated_indirect_draws.c:34:10: fatal error: shaders/generated_draws_spv.h: No such file or directory
   34 | #include "shaders/generated_draws_spv.h"
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
```

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21592>
 2023-02-28 17:09:32 +01:00
Tapani Pälli 75968398f3 anv: emit 3DSTATE_HS for each primitive on gfx12 
This is Wa_16011107343, same workaround as commit 880a3efe6c
but for gfx12.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21551>
 2023-02-28 08:07:01 +00:00
Emma Anholt d246948ce3 anv: Skip BTI RT flush if we're doing an op that doesn't use render targets. 
rt_flushes emitted on zink sauer.trace --loop=500 -2.02118% +/- 1.15992% (n=8).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21508>
 2023-02-27 21:44:56 +00:00
Emma Anholt 2bd304bc8f anv: Skip the RT flush when doing depth-only rendering. 
The spec citation says it's just for when the RT write message BTI might
point to a different RT, and if we don't have any color attachments then
we won't have one of those at all.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21508>
 2023-02-27 21:44:56 +00:00
Caio Oliveira c80268a20d intel/compiler: Mark various memory barriers intrinsics unreachable 
Now that both SPIR-V and GLSL are using scoped barriers, we can stop
handling the specialized ones.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3339>
 2023-02-27 20:24:01 +00:00
Yonggang Luo 669a68489d meson: Use sse2_arg and sse2_args to replace usage of c and c_sse2_args 
And now c_sse2_arg and c_sse2_args are remvoed

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21375>
 2023-02-27 13:50:11 +00:00
Mike Blumenkrantz 7c8a5f6e37 vulkan/wsi: switch to using an options struct for last param 
this makes adding values easier since the drivers won't need to be updated

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21447>
 2023-02-27 13:21:21 +00:00
Francisco Jerez 4420251947 intel/rt: Fix L3 bank performance bottlenecks due to SW stack stride alignment. 
Power-of-two SW stack sizes are prone to causing collisions in the
hashing function used by the L3 to map memory addresses to banks,
which can cause stack accesses from most DSSes to bottleneck on a
single L3 bank.  Fix it by padding the SW stack stride by a single
cacheline if it was a power of two.  This has been reported by Felix
DeGrood to improve Quake2 RTX performance by ~30% on DG2-512 in
combination with other RT patches Lionel Landwerlin has been working
on.

Many thanks to Felix DeGrood for doing much of the legwork and
providing several iterations of Q2RTX performance counter dumps which
eventually prompted me to consider the hash collision theory and
motivated this patch, and for providing additional performance counter
dumps confirming that there is no longer an appreciable imbalance in
traffic across L3 banks after this change.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21461>
 2023-02-26 11:48:33 -08:00
David Heidelberg b52917f9fc intel: use c_see2_arg instead of explicit -msse2 
This allows us to also inherit `-mfpmath=sse` added in previous commit.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21371>
 2023-02-25 15:34:33 +01:00
David Heidelberg 1851ca714b intel: enable -mfpmath=sse on x86 
It's not enabled by default until `-msse2` and -ffast-math is passed.
We pass only the `-msse2`. Let's align it with main `meson.build`.

See: https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html (-mfpmath).

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21371>
 2023-02-25 15:34:00 +01:00
Lionel Landwerlin 8441d565ec anv: remove assert typed write support when using NULL surface 
A number of apps hit this assert in debug mode.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21382>
 2023-02-25 09:20:01 +00:00
Iván Briano b71957635f anv: stop tracking color blend state in the pipeline 
Now that all color blend bits are dynamic, emit_cb_state() is doing
almost nothing and half of that is wrong.

In the case that color write enable is dynamic, at the time the pipeline
state is emitted, it sees all the color attachments as having write
disabled and stores the WriteDisabled bit for each channel.
When all dynamic state is flushed, we have the right values already but
the values recorded into the command buffer get ORed with the ones
stored in the pipeline, and so WriteDisabled tag along when they
shouldn't.

Since all disabled color attachments are handled already when dynamic
state is flushed, there's no point in doing so at pipeline creation
time too. And since the only other thing done by emit_cb_state() is
writing three hardcoded values, they might as well be taken care of in
the same place as everything else.

Fixes CTS from the future:
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_equation_*dynamic*
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_all_*

Fixes: fc3fd7c69e (anv: dynamic color write mask)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>
 2023-02-24 22:07:52 +00:00
Iván Briano dd5c6446b4 anv: fix testing for dynamic color blend bits 
Fixes: fc3fd7c69e (anv: dynamic color write mask)
Fixes: 9dc6bed9a1 (anv: dynamic state for logic op enable)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>
 2023-02-24 22:07:52 +00:00
Faith Ekstrand 96c832c47e spirv: Always emit deref_buffer_array_length intrinsics 
All the drivers have been converted to setting this option now except
imagination and they don't support SSBOs yet.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
 2023-02-24 20:37:10 +00:00
Faith Ekstrand 7594a64ebe hasvk: Drop our manual SSBO size handling 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
 2023-02-24 20:37:10 +00:00
Faith Ekstrand a1c82fa42f anv: Drop our manual SSBO size handling 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
 2023-02-24 20:37:10 +00:00
Sviatoslav Peleshko 07b57deea2 anv: Move WA MEDIA_VFE_STATE after stalling PIPE_CONTROL 
Fixes: bc612536 ("anv: Emit a dummy MEDIA_VFE_STATE before switching from GPGPU to 3D")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6172
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21472>
 2023-02-24 10:08:43 +00:00
Emma Anholt ae0e1eb0af ci/hasvk: Add a synchronization flake. 
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21366>
 2023-02-24 07:31:36 +00:00
Sviatoslav Peleshko 4bf38f5652 anv: Handle all fields in VkAccelerationStructureBuildRangeInfoKHR 
Add handling of primitiveOffset and firstVertex.

Fixes: f3ddfd81 ("anv: Build BVHs on the GPU with GRL")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8296
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21342>
 2023-02-24 07:08:05 +00:00
Caio Oliveira 8f3d0141de anv, hasvk: Align workaround address to 32B 
Not necessary but, all things being equal, be consistent with Iris.

Now that intel_debug_write_identifiers() already add the padding,
there's no need to include extra "+ 8" to the offset.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21479>
 2023-02-24 04:57:40 +00:00
Caio Oliveira ea0ec8c562 intel: Add extra zeros at the end of debug identifiers 
Add at least a full aligned uint64_t of zero padding at the end
to make the identifiers easier to spot.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21479>
 2023-02-24 04:57:40 +00:00
Caio Oliveira fb2a6248d2 hasvk: Update driver name in debug information 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21481>
 2023-02-24 00:41:09 +00:00
Tapani Pälli 880a3efe6c anv: implement emission of 3DSTATE_HS for Wa_1306463417 
We need to emit 3DSTATE_HS for each primitive with tessellation.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Tapani Pälli f8a1100ca1 anv: limit generated draws to pipelines without HS stage 
This is done for gfx11 specific workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Tapani Pälli 2028f1caa3 anv: emit 3DSTATE_HS in cmd_buffer_flush_gfx_state 
Patch packs 3DSTATE_HS state during pipeline creation but it
gets emitted only before 3DPRIMITIVE. We will later need this
to implement a workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21308>
 2023-02-23 19:30:03 +00:00
Chia-I Wu e97ed4fc89 anv: process utrace payloads on queue submission 
anv_QueuePresentKHR is not called by apps that do not use WSI.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21456>
 2023-02-23 18:06:16 +00:00
Väinö Mäkelä 2bef26ed04 ci/intel: Update hasvk HSW xfails 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:14 +00:00
Väinö Mäkelä d6d8edf9ae hasvk: Handle subpass self-dependencies for stencil shadow copies 
Always copying when dstAccessMask includes texture operations is not
optimal, but it's good enough.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:13 +00:00
Väinö Mäkelä d3162f97b5 hasvk: Mark VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL as stencil write optimal 
VK_KHR_synchronization2 added VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL, which
was not previously recognized by vk_image_layout_stencil_write_optimal.

Would close https://gitlab.freedesktop.org/mesa/mesa/-/issues/5578 if it
wasn't already closed.

Fixes: b996fa8efa ("anv: implement VK_KHR_synchronization2")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:13 +00:00
Väinö Mäkelä 79a58cb79b hasvk: Enable PixelShaderKillsPixel when omask is used 
From the Haswell PRM Vol. 2b, 3DSTATE_WM::Pixel Shader Kill Pixel:
    "This bit is required to be ENABLED in the following situations:
     - The API pixel shader program contains "killpix" or "discard"
       instructions, or other code in the pixel shader kernel that can
       cause the final pixel mask to differ from the pixel mask received
       on dispatch.
     - A sampler with chroma key enabled with kill pixel mode is used by
       the pixel shader.
     - Any render target has Alpha Test Enable or AlphaToCoverage Enable
       enabled.
     - The pixel shader kernel generates and outputs oMask."

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19876>
 2023-02-23 16:02:13 +00:00
Lionel Landwerlin ce68824bdf anv: fix invalid masking of 48bit address 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4d05be49c2 ("anv: implement vkCmdTraceRaysIndirect2KHR")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21486>
 2023-02-23 15:02:45 +00:00
José Roberto de Souza af994570f0 intel/blorp: Allocate only necessary amount of VERTEX_BUFFER_STATE 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>
 2023-02-23 14:27:30 +00:00
José Roberto de Souza a364f23a6c intel: Make gen12 URB space reservation dependent on compute engine presence 
Tigerlake PRM: Volume 2c: Command Reference: Registers Part 2 - Registers M through Z
RCU_MODE :: Compute Engine Enable

   This bit indicates if Compute Engine (a.k.a Dual Context or Multi
   Context) is enabled or not. This bit must be treated as global
   control for enabling and disabling of compute engine. Hardware
   allocates required resources for the compute engine based on this
   bit.
   ....
   HW reserves 4KB of URB space...

Right now no gen12 platform has Dual Context enabled in kernel side,
exposing a compute engine but that can change, so here adding
has_compute_engine to intel_device_info and only reserving URB space
if compute engine is available.

While at it also fixing the error path when pb_slabs_init() fails.

Bspec: 46034
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031>
 2023-02-23 14:27:30 +00:00
Eric Engestrom fbd644c59d meson: replace vk_wsi_args with dependencies to let meson take care of transitivity 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19497>
 2023-02-23 09:42:46 +00:00
Marcin Ślusarz 512126b26d intel/compiler: remove unused field from fs_thread_payload 
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20957>
 2023-02-23 08:04:24 +00:00
Konstantin Seurer 6242fe3923 anv: Use vk_acceleration_structure 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21047>
 2023-02-22 11:58:57 +00:00
Marcin Ślusarz e29a964d02 intel/compiler/mesh: follow the type of offset variable 
This allows copy propagation to kick in, decreasing the overall
number of generated instructions.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21098>
 2023-02-21 11:10:24 +00:00
Marcin Ślusarz 15afb8dcc6 intel/compiler/mesh: apply URB payload mask once per program 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21098>
 2023-02-21 11:10:23 +00:00
Daniel Schürmann 2bb369dd8d nir: add assertions that loops don't have a Continue Construct 
Hoping that I didn't miss any, this *should* add assertions
to all functions and passes which explicitly handle 'nir_loop'.

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13962>
 2023-02-21 10:41:11 +00:00