AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
180,251 Commits 1 Branch 0 Tags
0dd5378ffe9cc7c3eee4e5b400a2bb30c759efb7
Commit Graph

10573 Commits

Author SHA1 Message Date
Hyunjun Ko 91235092ab anv/image: allow VK_IMAGE_CREATE_ALIAS_BIT with a private binding. 
when the image is for video decoding.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
 2023-05-19 06:15:01 +00:00
Hyunjun Ko 23c338af5d anv/image: allocate mv storage buffers for h265 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
 2023-05-19 06:15:01 +00:00
Hyunjun Ko b4b31828e0 anv/image: Add a surface usage bit for video decoding 
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
 2023-05-19 06:15:01 +00:00
Hyunjun Ko d5f8265e05 intel/genxml: add a command VD_CONTROL_STATE to gen12/125 
It's essentially needed to execute hevc decoding on gen12.

Note that we set HCP by default.
 - Command OpCode : VDENC(1), HCP(7), AVP(3)
 - SubOpcode      : HCP(10), VDENC(11)

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
 2023-05-19 06:15:01 +00:00
Hyunjun Ko 27dcd18210 intel/genxml: align some fields on gen9/11/12/125 with media driver. 
Most of them are length of each instruction and the rest are
some corrections on specific gens.

v1. Added a default value to DWordLength of each instruction.
( Lionel Landwerlin <lionel.g.landwerlin@intel.com> )

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
 2023-05-19 06:15:01 +00:00
Hyunjun Ko b3a1a8c617 intel/genxml: conform some fields to each other gen. 
There are same fields across gens but the existing xmls are not exactly same,
which needs to be fixed.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
 2023-05-19 06:15:01 +00:00
Hyunjun Ko 44bc651aba intel/genxml: fix num bits of some MOCS fields 
Actually the first bit is a bit of protected mask (or reserved)
and the next 6 bits are for MOCS but they are being handled together
currently in isl_device_setup_mocs. So we need to fix some MOCS fields
defined as 6 bits to 7 bits.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22202>
 2023-05-19 06:15:01 +00:00
Rohan Garg 2e8b1f6d1c anv: drop duplicate checks when setting the compressed bit 
We need compression tracking for full resolves and at the moment only
CCS_E has full resolves.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22737>
 2023-05-18 23:20:49 +00:00
Rohan Garg 6b8fe32322 intel: infer scalar'ness locally for brw_vectorize_lower_mem_access 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23098>
 2023-05-18 15:46:06 +02:00
Rohan Garg 3a8f5c2783 intel: update comments about non-existent function parameter 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23098>
 2023-05-18 15:46:06 +02:00
Rohan Garg a15cc833f9 intel: drop unused is_scalar function parameter in brw_nir_apply_key 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23098>
 2023-05-18 15:46:06 +02:00
Rohan Garg 212810ac8a intel: infer scalar'ness locally for brw_postprocess_nir 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23098>
 2023-05-18 15:46:06 +02:00
Kenneth Graunke 78a195f252 intel/compiler: Postpone most int64 lowering to brw_postprocess_nir 
Float conversions continue to be lowered early at the same time as
nir_lower_doubles, which we run early so we don't have to run it for
every shader key variant.  However, all other int64 lowering is now
done late, after nir_opt_load_store_vectorize(), allowing it to
comprehend basic arithmetic on 64-bit addresses.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23064>
 2023-05-18 10:48:50 +00:00
Alyssa Rosenzweig c7861fe1f2 nir: Drop unused argument from nir_ssa_dest_init_for_type 
Similar to nir_ssa_dest_init, but with fewer call sites to churn through.

This was done with the help of Coccinelle:

   @@
   expression A, B, C, D;
   @@

   -nir_ssa_dest_init_for_type(A, B, C, D);
   +nir_ssa_dest_init_for_type(A, B, C);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
 2023-05-17 23:46:16 +00:00
Alyssa Rosenzweig 01e9ee79f7 nir: Drop unused name from nir_ssa_dest_init 
Since 624e799cc3 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:

    @@
    expression A, B, C, D, E;
    @@

    -nir_ssa_dest_init(A, B, C, D, E);
    +nir_ssa_dest_init(A, B, C, D);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
 2023-05-17 23:46:16 +00:00
Lionel Landwerlin 1a89b1a301 anv: mark images compressed for untracked layout/access 
Most of the compressed writes are tracked by the driver, for
instances :
   - blorp writes
   - render target writes

But we don't have any tracking for storage images (which have gained
compression support on DG2+). So inspect the layout transition and
when we see a layout/access that can do writes outside of our driver
tracking, update the image state tracking.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8946
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22988>
 2023-05-17 22:01:31 +00:00
Daniel Schürmann 8bfd18b8c5 vulkan/pipeline_cache: don't log warnings for client-invisible caches 
Fixes: d3f06cf5ce ('vulkan/pipeline_cache: don't log warnings for internal caches')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22986>
 2023-05-17 20:40:12 +00:00
Sagar Ghuge 688ee02864 anv: Set CS stall bit during HIZ_CCS_WT surface fast clear 
It make sense to enable CS stall so that it guarantees that the fast
clear will start after tile cache flush has completed.

cc: mesa-stable
closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9030

Fixes: e488773b ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments"
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23063>
 2023-05-17 10:05:34 -07:00
Lionel Landwerlin 7f7b2fc53a anv: put private binding BOs into execlists 
Not doing so all the reads/writes go to the scratch page on i915.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f9fa09ec92 ("anv/image: Add ANV_IMAGE_MEMORY_BINDING_PRIVATE")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22957>
 2023-05-17 14:59:14 +00:00
Rohan Garg 42ed0f0356 anv: drop duplicated nir_opt_dce passes 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23075>
 2023-05-17 13:26:41 +00:00
Rohan Garg b2e733a8ed anv: use the common vulkan runtime to do the heavy lifting 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23075>
 2023-05-17 13:26:41 +00:00
Alyssa Rosenzweig c323762f9f treewide: Stop lowering legacy atomics 
There are no more producers of legacy atomics so these calls are inert.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
 2023-05-16 22:36:21 +00:00
Alyssa Rosenzweig e7bb53467b intel: Produce unified atomics 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
 2023-05-16 22:36:21 +00:00
Lionel Landwerlin ec4619a5e9 intel/devinfo: call intel_device_info_init_was only once 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8958

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22862>
 2023-05-16 19:32:41 +00:00
Lionel Landwerlin 9ebd553fc2 intel/devinfo: allow -p to take a pci-id in hexa 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22862>
 2023-05-16 19:32:41 +00:00
Lionel Landwerlin fce55ffb7d intel/devinfo: printout on stdout 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22862>
 2023-05-16 19:32:41 +00:00
Iván Briano a15bffe2b8 anv: enable the GPL feature based on whether the extension is supported 
Instead of checking if the very same bit we want to enable is already
enabled, which obviously doesn't work.

Fixes: fbc0e74bda ("anv: enable graphics pipeline libraries by default")

Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23039>
 2023-05-16 02:01:30 +00:00
Nanley Chery f220f3fdae intel/blorp: Assert an 8bpp fast clear restriction 
We can't do fast clear operations on some LODs of 8bpp surfaces. Add an
assertion to BLORP to protect against drivers attempting to do this.

This assertion was successfully hit with some local modifications to
iris and with the piglit test case, "generatemipmap-base-change format".

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7301
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22857>
 2023-05-15 19:54:02 +00:00
Zhang, Jianxun 7f84eee3c6 intel/isl: Fix map between sRGB and linear formats 
Some SRGB formats don't get the expected linear counterparts in
isl_format_srgb_to_linear() in the generated isl_format_layout.c.

The replace() of string in python returns the unchanged input
string when no replacement occurred, so the first rule
('_SRGB', '') returns the original SRGB format name that passes
the following check unintendedly.

Another quirk is needed for a pair of formats not following
the patterns of other formats.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22247>
 2023-05-15 18:49:13 +00:00
Lionel Landwerlin 952a523abb intel: switch over to unified atomics 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23004>
 2023-05-15 16:32:21 +00:00
Konstantin Seurer 0cf22f9af3 nir: Make rq_load committed src an index 
committed has to be a constant so there is no need to have a src and
depend on constant folding to remove the i2b.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>
 2023-05-14 17:28:40 +00:00
Felix DeGrood 142c4f5abc intel: Secondary CB print primary CB's renderpass 
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
 2023-05-12 21:15:09 +00:00
Felix DeGrood 07ec481cd8 intel: batch consecutive dispatches into implicit renderpasses 
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
 2023-05-12 21:15:09 +00:00
Felix DeGrood 82f6a477f3 intel: refactor INTEL_MEASURE pointer dumping 
Refactor framebuffer to renderpass to mirror previous INTEL_MEASURE
changes.

We dump hashes/pointers for shaders and framebuffer/renderpass.
Reduce from 64bit to 32bit pointers. We don't benefit from the
extra precision and reduced output size is convenient.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
 2023-05-12 21:15:09 +00:00
Felix DeGrood e2dfab5c96 anv: re-enable RT data in INTEL_MEASURE 
Per-RenderTarget analysis was removed from anv's INTEL_MEASURE
previously, probably after switching to dynamic rendering model.
Restore capability by tracking count of beginRenderPass calls.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
 2023-05-12 21:15:09 +00:00
Felix DeGrood f783f581a8 anv: fix INTEL_MEASURE on MTL 
Ensure counter buffer is coherent. Required for MTL which changes
coherence policy.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
 2023-05-12 21:15:09 +00:00
Tapani Pälli b0b6811b9b anv: handle missing astc for gfx125 in CreateImageView 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22818>
 2023-05-12 06:59:34 +00:00
Iván Briano d41b83e1ca hasvk: avoid assert due to unsupported format 
Fixes: 0a4c92b646 ("hasvk: Use the common vk_ycbcr_conversion object")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9011
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22978>
 2023-05-11 19:48:39 -07:00
Nanley Chery e930ad6017 anv: Enable MCS init with ISL_AUX_OP_AMBIGUATE 
Up until now, we have been initializing MCS with fast clears. This is
mostly safe, but there's a corner case that can be an issue.

The issue is with a workaround for MCS that requires the sampler not see
any fast-cleared blocks for certain surfaces (14013111325). Even though
we have been initializing MCS with fast clears, we expect most
applications to be safe because we expect that they would only sample
the samples they've rendered to previously (and the render would've
removed the fast-cleared blocks). In other words we don't expect that
apps would transition from VK_IMAGE_LAYOUT_UNDEFINED to
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL and start sampling immediately.

If an application took the unexpected path of sampling undefined
samples, it's possible they'd hit the issue described in the workaround.

Fix this corner case by using an ambiguate to initialize MCS.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
 2023-05-11 23:41:16 +00:00
Nanley Chery 5b01a0ac47 anv: Drop the MCS initialization performance warning 
The comment above the warning explains that not all bit patterns are
necessarily valid. While we're at it, fix a typo in that comment.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
 2023-05-11 23:41:16 +00:00
Nanley Chery bba4d850c2 intel: Implement ISL_AUX_OP_AMBIGUATE for MCS 
Implement the ambiguate operation for MCS. This clears MCS layers with a
sample-dependent "uncompressed" value that tells the sampler to go look
at the main surface.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
 2023-05-11 23:41:16 +00:00
Nanley Chery a1ed41dec7 intel/isl: Bump the MCS halign value for BDW+ 
Select a horizontal alignment value that matches the main MSAA surface.

We need a valid horizontal alignment to perform MCS ambiguates. The
halign value doesn't actually affect test behavior, but it is validated
by isl_surf_fill_state. We currently have an invalid halign for gfx125.
This patch fixes that.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
 2023-05-11 23:41:16 +00:00
Matt Turner 435a607909 intel: Disable shader cache when executing intel_clc during the build 
With the shader cache enabled, intel_clc attempts to write to ~/.cache.
Many distributions' build systems limit file-system access, and will
kill the process thus causing the build to fail.

Fixes: 639665053f ("anv/grl: Build OpenCL kernels")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22968>
 2023-05-11 23:00:01 +00:00
Chia-I Wu eaf1776586 anv,hasvk: android ahb is not always exportable 
anv_ahb_format_for_vk_format needs to know the format at least.  There
is no guarantee that AHardwareBuffer_allocate will succeed, but we are
reluctant to check with AHardwareBuffer_isSupported which may
test-allocate internally and is expensive.

v2: add anv_ahb_format_for_vk_format to anv_android_stubs.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
 2023-05-11 22:18:03 +00:00
Chia-I Wu 47b37651f8 vulkan: add vk_image_format_to_ahb_format 
There should be no functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
 2023-05-11 22:18:03 +00:00
Chia-I Wu 380180516c anv,hasvk,radv: do not fall back to AHARDWAREBUFFER_FORMAT_BLOB 
When allocating a VkDeviceMemory exportable as AHB, it seems incorrect
to fall back to AHARDWAREBUFFER_FORMAT_BLOB when the image has no known
AHB format.  We should fail the allocation instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
 2023-05-11 22:18:03 +00:00
Chia-I Wu 50e703f347 vulkan: add vk_ahb_format_to_image_format 
There should be no functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
 2023-05-11 22:18:02 +00:00
Chia-I Wu 2bbe0462e8 vulkan: define inline stubs when android api level < 26 
This allows us to reduce ANDROID #ifdef's.

v2: always include vk_android.h in radv_formats.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
 2023-05-11 22:18:02 +00:00
Chia-I Wu f81dce9bcc vulkan: rename vk_image::ahardware_buffer_format 
Rename it to ahb_format.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
 2023-05-11 22:18:02 +00:00
Chia-I Wu 5561abcb2c vulkan: make sure vk_image_view::format is never UNDEFINED 
Remove redundant override in anv and hasvk as well.

Fixed
android.graphics.cts.BasicVulkanGpuTest#testBasicBufferImportAndRenderingExternalFormat
for radv.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
 2023-05-11 22:18:02 +00:00